Abstract: A method is provided for hardware acceleration of a neural network model of an electronic equipment and a device thereof. The method includes: obtaining data to be identified and a configuration parameter for the neural network model of the first electronic equipment; proceeding the hardware acceleration of a convolution calculation matched with the neural network model of the first electronic equipment for the data to be identified according to the configuration parameter, and generating a convolution result of the neural network model of the first electronic equipment for the data to be identified. The invention can support a neural network model established by various open source development environments, and also support a user-defined neural network model; when the algorithm of the neural network model is updated, only the parameters of the first electronic device need to be reconfigured without changing the hardware.

Abstract: A method for improving OpenCL hardware execution efficiency described in this invention comprises the following steps: compiling a kernel implemented in OpenCL, generating Verilog code with a high-level synthesis tool; analyzing the interfaces of auto-generated Verilog code, recording signals, timing sequence, and function of the interfaces; manually modifying and optimizing the Verilog code; inserting a file replacement command in the script responsible for flow control, replacing the auto-generated code with the optimized Verilog code; rerunning OpenCL compiler and generating an ultimate FPGA configuration file. The invention makes manual optimization of the auto-generated Verilog code becomes possible, by parsing the compilation flow of OpenCL environment and analyzing the structure and interfaces of the auto-generated Verilog code.

Abstract: A method for improving OpenCL hardware execution efficiency described in this invention comprises the following steps: compiling a kernel implemented in OpenCL, generating Verilog code with a high-level synthesis tool; analyzing the interfaces of auto-generated Verilog code, recording signals, timing sequence, and function of the interfaces; manually modifying and optimizing the Verilog code; inserting a file replacement command in the script responsible for flow control, replacing the auto-generated code with the optimized Verilog code; rerunning OpenCL compiler and generating an ultimate FPGA configuration file. The invention makes manual optimization of the auto-generated Verilog code becomes possible, by parsing the compilation flow of OpenCL environment and analyzing the structure and interfaces of the auto-generated Verilog code.