Patents by Inventor Ailian Zhao
Ailian Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130242Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming at least one magnetic tunnel junction (MTJ) stack on top of a supporting structure; forming a conformal liner surrounding a sidewall of the MTJ stack; forming a first dielectric layer surrounding the conformal liner; selectively forming a metal oxide layer on top of the conformal liner and the first dielectric layer, the metal oxide layer having at least a first opening that exposes a top surface of the MTJ stack; and forming a top contact contacting the top surface of the MTJ stack through the first opening in the metal oxide layer. An MRAM structure formed thereby is also provided.Type: ApplicationFiled: October 13, 2022Publication date: April 18, 2024Inventors: Ailian Zhao, Wu-Chang Tsai, Ashim Dutta, Chih-Chao Yang
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Publication number: 20240099035Abstract: A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Inventors: Wu-Chang Tsai, Ailian Zhao, Ashim Dutta, Chih-Chao Yang
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Publication number: 20240090235Abstract: An apparatus comprising a backside power distribution network; a backside power rail joined to the backside power distribution network; and a backside contact via that couples at least one front end of line transistor to the backside power rail; wherein the backside contact via comprises a pillar based memory device.Type: ApplicationFiled: September 12, 2022Publication date: March 14, 2024Inventors: Wu-Chang Tsai, Alexander Reznicek, Michael Rizzolo, Ailian Zhao
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Patent number: 10147876Abstract: Systems and methods for providing a phase change memory that includes a phase change material, such as a chalcogenide material, in series with a heating element that comprises multiple thermal interfaces are described. The multiple thermal interfaces may cause the heating element to have a reduced bulk thermal conductivity or a lower heat transfer rate across the heating element without a corresponding reduction in electrical conductivity. The phase change material may comprise a germanium-antimony-tellurium compound or a chalcogenide glass. The heating element may include a plurality of conducting layers with different thermal conductivities. In some cases, the heating element may include two or more conducting layers in which the conducting layers comprise the same electrically conductive material or compound but are deposited or formed using different temperatures, carrier gas pressures, flow rates, and/or film thicknesses to create thermal interfaces between the two or more conducting layers.Type: GrantFiled: August 31, 2017Date of Patent: December 4, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Lidu Huang, Mac D. Apodaca, Toshiki Hirano, Ailian Zhao, Guy Charles Wicker, Federico Nardi
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Patent number: 9646929Abstract: A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.Type: GrantFiled: June 13, 2013Date of Patent: May 9, 2017Assignee: GLOBALFOUNDRIES, INC.Inventors: Hsueh-Chung Chen, Chiahsun Tseng, Chun-Chen Yeh, Ailian Zhao
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Patent number: 9330965Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.Type: GrantFiled: August 27, 2015Date of Patent: May 3, 2016Assignees: International Business Machines Corporation, Global Foundries Inc.Inventors: Hsueh-Chung Chen, Yongan Xu, Yunpeng Yin, Ailian Zhao
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Patent number: 9257334Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.Type: GrantFiled: August 27, 2015Date of Patent: February 9, 2016Assignees: International Business Machines Corporation, Global Foundries IncInventors: Hsueh-Chung Chen, Yongan Xu, Yunpeng Yin, Ailian Zhao
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Publication number: 20150371896Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.Type: ApplicationFiled: August 27, 2015Publication date: December 24, 2015Inventors: Hsueh-Chung Chen, Yongan Xu, Yunpeng Yin, Ailian Zhao
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Patent number: 9219007Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.Type: GrantFiled: June 10, 2013Date of Patent: December 22, 2015Assignees: International Business Machines Corporation, Global Foundries Inc.Inventors: Hsueh-Chung Chen, Yongan Xu, Yunpeng Yin, Ailian Zhao
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Publication number: 20150364372Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.Type: ApplicationFiled: August 27, 2015Publication date: December 17, 2015Inventors: Hsueh-Chung Chen, Yongan Xu, Yunpeng Yin, Ailian Zhao
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Patent number: 9054052Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.Type: GrantFiled: May 28, 2013Date of Patent: June 9, 2015Assignee: GLOBAL FOUNDRIES INC.Inventors: Nicholas Vincent Licausi, Errol Todd Ryan, Ming He, Moosung M. Chae, Kunaljeet Tanwar, Larry Zhao, Christian Witt, Ailian Zhao, Sean X. Lin, Xunyuan Zhang
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Publication number: 20150155238Abstract: A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.Type: ApplicationFiled: January 29, 2015Publication date: June 4, 2015Applicant: GLOBALFOUNDRIES, INC.Inventors: Hsueh-Chung Chen, Chiahsun Tseng, Chun-Chen Yeh, Ailian Zhao
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Patent number: 8932934Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.Type: GrantFiled: May 28, 2013Date of Patent: January 13, 2015Assignee: Global Foundries Inc.Inventors: Moosung M. Chae, Errol Todd Ryan, Nicholas Vincent Licausi, Christian Witt, Ailian Zhao, Ming He, Sean X. Lin, Xunyuan Zhang, Kunaljeet Tanwar
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Publication number: 20140367826Abstract: A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.Type: ApplicationFiled: June 13, 2013Publication date: December 18, 2014Inventors: Hsueh-Chung Chen, Chiahsun Tseng, Chun-Chen Yeh, Ailian Zhao
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Publication number: 20140363969Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.Type: ApplicationFiled: June 10, 2013Publication date: December 11, 2014Applicants: Globalfoundries Inc., International Business Machines CorporationInventors: Hsueh-Chung Chen, Yongan Xu, Yunpeng Yin, Ailian Zhao
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Publication number: 20140353835Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.Type: ApplicationFiled: May 28, 2013Publication date: December 4, 2014Inventors: Moosung M. CHAE, Errol Todd RYAN, Nicholas Vincent LICAUSI, Christian WITT, Ailian ZHAO, Ming HE, Sean X. LIN, Xunyuan ZHANG, Kunaljeet TANWAR
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Publication number: 20140353805Abstract: A process is provided for the removal of contaminants from a semiconductor device, for example, removing contaminants from pores of an ultra-low k film. In one aspect, a method includes: providing a dielectric layer with contaminant-containing pores and exposing the dielectric layer to a supercritical fluid. The supercritical fluid can dissolve and remove the contaminants. In another aspect, an intermediate semiconductor device structure is provided that contains a dielectric layer with contaminant-containing pores and a supercritical fluid within the pores. In another aspect, a semiconductor device structure with a dielectric layer containing uncontaminated pores is provided.Type: ApplicationFiled: May 28, 2013Publication date: December 4, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Errol Todd RYAN, Moosung M. CHAE, Larry ZHAO, Kunaljeet TANWAR, Nicholas Vincent LICAUSI, Christian WITT, Ailian ZHAO, Ming HE, Sean X. LIN, Xunyuan ZHANG
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Publication number: 20140353802Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.Type: ApplicationFiled: May 28, 2013Publication date: December 4, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Nicholas Vincent LICAUSI, Errol Todd RYAN, Ming HE, Moosung M. CHAE, Kunaljeet TANWAR, Larry ZHAO, Christian WITT, Ailian ZHAO, Sean X. LIN, Xunyuan ZHANG
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Patent number: 8455298Abstract: A method for fabricating a memory device includes depositing a phase-change and/or a resistive change material. The memory device is formed photolithographically using sixteen or fewer masks.Type: GrantFiled: August 18, 2009Date of Patent: June 4, 2013Assignee: Contour Semiconductor, Inc.Inventors: Mac D. Apodaca, Ailian Zhao, Jenn C. Chow, Thomas Brown, Lisa Ceder
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Publication number: 20100096610Abstract: A memory cell includes a current-steering device, a phase-change material disposed thereover, and a heating element and/or a cooling element.Type: ApplicationFiled: October 19, 2009Publication date: April 22, 2010Inventors: Hsingya A. Wang, Daniel R. Shepard, Mac D. Apodaca, Ailian Zhao