Abstract: A circuit. The circuit includes a first transmitter circuit having a first input terminal arranged to receive a first input data and a first node arranged to transmit a first intermediate data corresponding to the first input data, a first receiver circuit including a second node arranged to receive the first intermediate data and a first output terminal arranged to produce a first output data corresponding to the first input data, a second transmitter circuit including a second input terminal arranged to receive a second input data and the second node that is further arranged to transmit a second intermediate data corresponding to the second input data; and a second receiver circuit including the first node and a second output terminal, the first node further arranged to receive the second intermediate data, and the second output terminal arranged to produce a second output data corresponding to the second input data.

Abstract: A circuit is disclosed. The circuit includes a modulator circuit referenced to a first ground and arranged to receive at least a first status identifier signal and a second status identifier signal, a pulse width modulated (PWM) signal and a first bitstream signal, and in response generate a modulated signal; an isolation capacitor coupled between to the modulator circuit and a demodulator circuit, wherein the modulator circuit is arranged to transmit the modulated signal through the isolation capacitor to the demodulator circuit; and a clock generator circuit arranged to generate a clock signal (CK0), where the PWM signal and the first bitstream signal are synchronized with CK0; and where the demodulator circuit is referenced to a second ground and is arranged to receive the modulated signal and generate output signals corresponding to the first and second status identifier signals, the PWM signal and the first bitstream signal.

Abstract: A circuit is disclosed. The circuit includes a transmitter having an input terminal arranged to receive input data and a transmission node arranged to transmit intermediate data corresponding to the input data, and a receiver having a receive node arranged to receive the intermediate data and an output terminal arranged to produce output data corresponding to the input data, the receiver further including a dV/dt detector circuit coupled to the receive node and arranged to stop the production of the output data at the output terminal when the dV/dt detector circuit detects a rate of change of voltage with respect to time greater than a predetermined threshold.

Abstract: A circuit is disclosed. The circuit includes a transmitter having an input terminal arranged to receive input data and a transmission node arranged to transmit intermediate data corresponding to the input data, and a receiver having a receive node arranged to receive the intermediate data and an output terminal arranged to produce output data corresponding to the input data, the receiver further including a dV/dt detector circuit coupled to the receive node and arranged to stop the production of the output data at the output terminal when the dV/dt detector circuit detects a rate of change of voltage with respect to time greater than a predetermined threshold.

Abstract: The invention relates to a digital isolator comprising a logic module (20) for receiving an input signal D, and providing command signals (41, 42) to sawtooth modulators. A first sawtooth modulator provides a first sawtooth signal at a node A1 comprising a fast rising edge triggered by a rising edge of a control signal, followed by a slow falling edge, when D equals 1 and comprises a fast falling edge triggered by a rising edge of a control signal, followed by a slow rising edge, when D equals 0. A second sawtooth modulator provides a second sawtooth signal at node A2, inverted with respect to first sawtooth signal. Isolation capacitors (61, 62) are connected to nodes A1 and A2 and are used as isolation barrier and as part of a high-pass filter together with dipoles Z1 and Z2. Threshold comparators (121, 122) provide the output signals S and R.

Abstract: A digital isolator. The digital isolator a logic module for receiving an input signal D, and providing command signals to first and second sawtooth modulators. The first sawtooth modulator can provide a first sawtooth signal at a node A1 having a fast rising edge triggered by a rising edge of a control signal, followed by a slow falling edge, when D equals 1 and having a fast falling edge triggered by a rising edge of a control signal, followed by a slow rising edge, when D equals 0. A second sawtooth modulator provides a second sawtooth signal at node A2, inverted with respect to first sawtooth signal. Isolation capacitors connected to nodes A1 and A2 can be used as isolation barrier and as part of high-pass filters together with dipoles Z1 and Z2.

Abstract: A circuit is disclosed. The circuit includes a transmitter having an input terminal arranged to receive input data and a transmission node arranged to transmit intermediate data corresponding to the input data, and a receiver having a receive node arranged to receive the intermediate data and an output terminal arranged to produce output data corresponding to the input data, the receiver further including a dV/dt detector circuit coupled to the receive node and arranged to stop the production of the output data at the output terminal when the dV/dt detector circuit detects a rate of change of voltage with respect to time greater than a predetermined threshold.

Abstract: The invention relates to a digital isolator comprising a logic module (20) for receiving an input signal D, and providing command signals (41, 42) to sawtooth modulators. A first sawtooth modulator provides a first sawtooth signal at a node A1 comprising a fast rising edge triggered by a rising edge of a control signal, followed by a slow falling edge, when D equals 1 and comprises a fast falling edge triggered by a rising edge of a control signal, followed by a slow rising edge, when D equals 0. A second sawtooth modulator provides a second sawtooth signal at node A2, inverted with respect to first sawtooth signal. Isolation capacitors (61, 62) are connected to nodes A1 and A2 and are used as isolation barrier and as part of a high-pass filter together with dipoles Z1 and Z2. Threshold comparators (121, 122) provide the output signals S and R.

Abstract: The present invention provides a polymer composite material structure comprising at least one layer of a foamed polymer composite material comprising a foamed polymer matrix and 0.1 wt % to 6 wt % carbon based conductive loads, such as e.g. carbon nanotubes, dispersed in the foamed polymer matrix. The polymer composite material structure according to embodiments of the present invention shows good shielding and absorbing properties notwithstanding the low amount of carbon based conductive loads. The present invention furthermore provides a method for forming a polymer composite material structure comprising carbon based conductive loads.