Abstract: The present disclosure provides a self-aligned two-time forming method capable of preventing sidewalls from being deformed, comprises sequentially growing a first silicon nitride layer, a first silicon oxide layer, a titanium nitride layer, a second silicon oxide layer, a second silicon nitride layer and a polysilicon layer on a via layer from bottom to top; defining a pattern by using the polysilicon layer as a hard mask, and etching the second silicon nitride layer to an upper surface of the second silicon oxide layer to form a plurality of silicon nitride pattern structures from the second silicon nitride layer; forming sidewalls on sidewalls of the plurality of silicon nitride pattern structures; removing the silicon nitride pattern structures in the sidewalls; etching the silicon nitride layer and the titanium nitride layer by using the sidewalls as a hard mask to form a titanium nitride pattern structure.

Abstract: A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Abstract: A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to educe a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Abstract: A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Abstract: A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.