Patents by Inventor Aipeng Shu

Aipeng Shu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9252114
    Abstract: A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.
    Type: Grant
    Filed: November 23, 2014
    Date of Patent: February 2, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
  • Patent number: 9214413
    Abstract: A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound.
    Type: Grant
    Filed: November 23, 2014
    Date of Patent: December 15, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
  • Publication number: 20150243623
    Abstract: A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.
    Type: Application
    Filed: November 23, 2014
    Publication date: August 27, 2015
    Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
  • Publication number: 20150243586
    Abstract: A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound.
    Type: Application
    Filed: November 23, 2014
    Publication date: August 27, 2015
    Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
  • Patent number: 9024427
    Abstract: A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the supporting surfaces of the stairs. The columnar part, the stairs and the IC dies can be encapsulated with a mold compound.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: May 5, 2015
    Assignee: Freescale Semiconductor. Inc
    Inventors: Huan Wang, Aipeng Shu, Shu An Yao
  • Publication number: 20140284805
    Abstract: A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the supporting surfaces of the stairs. The columnar part, the stairs and the IC dies can be encapsulated with a mold compound.
    Type: Application
    Filed: February 11, 2014
    Publication date: September 25, 2014
    Inventors: Huan Wang, Aipeng Shu, Shu An Yao