Patents by Inventor Aira Lourdes VILLAMOR

Aira Lourdes VILLAMOR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818582
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include forming, with a laser, a groove in the signal lead, the groove having a first sidewall and a second sidewall, and applying solder plating to the signal lead, including the first sidewall and the second sidewall of the groove. The method can further include separating, at the groove, the signal lead into a first portion and a second portion, such that the second portion of the signal lead is separated from the metal leadframe structure.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 27, 2020
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes Villamor, Erwin Victor Cruz, Geraldine Suico, Silnore Sabando
  • Publication number: 20200083148
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include forming, with a laser, a groove in the signal lead, the groove having a first sidewall and a second sidewall, and applying solder plating to the signal lead, including the first sidewall and the second sidewall of the groove.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes VILLAMOR, Erwin Victor CRUZ, Geraldine SUICO, Silnore SABANDO
  • Patent number: 10483192
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include encapsulating at least a portion of the semiconductor device and at least a portion of the leadframe structure in a molding compound. At least a segment of the signal lead can be exposed outside the molding compound. A surface of the molding compound can define a primary plane of the packaged semiconductor device. The method can further include forming, with a laser, a groove in the segment, applying solder plating to the segment, including the groove, and separating, at the groove, the segment into a first portion and a second portion, such that the second portion of the segment is separated from the leadframe structure.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: November 19, 2019
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes Villamor, Erwin Victor Cruz, Geraldine Suico, Silnore Sabando
  • Publication number: 20190348290
    Abstract: A method of singulating a silicon carbide (SiC) semiconductor wafer can include defining a cut within the silicon carbide (SiC) semiconductor wafer by performing a partial dicing operation where the SiC semiconductor wafer is aligned along a plane and the cut has a depth less than a first thickness of the SiC semiconductor wafer. The cut is aligned along a vertical direction orthogonal to the plane such that a portion of the SiC semiconductor wafer has a second thickness that extends between a bottom of the cut and an outer surface of the SiC semiconductor wafer. The method can further include defining a cleave, by performing a cleaving operation, through the portion of the SiC semiconductor wafer having the second thickness. The cleave can be aligned with the cut and extending to the outer surface of the SiC semiconductor wafer.
    Type: Application
    Filed: May 9, 2018
    Publication date: November 14, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Aira Lourdes VILLAMOR
  • Publication number: 20180269138
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include encapsulating at least a portion of the semiconductor device and at least a portion of the leadframe structure in a molding compound. At least a segment of the signal lead can be exposed outside the molding compound. A surface of the molding compound can define a primary plane of the packaged semiconductor device. The method can further include forming, with a laser, a groove in the segment, applying solder plating to the segment, including the groove, and separating, at the groove, the segment into a first portion and a second portion, such that the second portion of the segment is separated from the leadframe structure.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes VILLAMOR, Erwin Victor CRUZ, Geraldine SUICO, Silnore SABANDO
  • Patent number: 9978668
    Abstract: In a general aspect, a packaged semiconductor device can include a semiconductor device and a metal leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The device can also include a molding compound encapsulating at least a portion of the metal leadframe structure. At least a portion of the signal lead can be exposed outside the molding compound. The device can further include a solder plating disposed on exposed portions of the metal leadframe structure. In the device, a flank of the signal lead can have a surface area. At first portion of the surface area of the flank can be defined by the solder plating, and a second portion of the surface area of the flank can be defined by exposed metal of the metal leadframe structure. A perimeter of a surface of the exposed metal can have at least one curved edge.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: May 22, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Aira Lourdes Villamor, Erwin Victor Cruz, Geraldine Suico, Silnore Sabando
  • Patent number: 9685398
    Abstract: In a general aspect, a packaged semiconductor device can include a semiconductor die having at least a first terminal on a first side of the semiconductor die and a second terminal on a second side of the semiconductor die. The device can include a leadframe portion electrically coupled to the first terminal of the semiconductor die and a clip portion electrically coupled to the second terminal of the semiconductor die. The device can include a molding compound. A surface of the leadframe portion and a first surface of the molding compound can define at least a portion of a first surface of the device. A surface of the clip portion and a second surface of the molding compound can define at least a portion of a second surface of the device that is parallel to the first surface of the device.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: June 20, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Margie Rios, Aira Lourdes Villamor, Maria Cristina Estacio, Armand Vincent Jereza
  • Publication number: 20160284628
    Abstract: In a general aspect, a packaged semiconductor device can include a semiconductor die having at least a first terminal on a first side of the semiconductor die and a second terminal on a second side of the semiconductor die. The device can include a leadframe portion electrically coupled to the first terminal of the semiconductor die and a clip portion electrically coupled to the second terminal of the semiconductor die. The device can include a molding compound. A surface of the leadframe portion and a first surface of the molding compound can define at least a portion of a first surface of the device. A surface of the clip portion and a second surface of the molding compound can define at least a portion of a second surface of the device that is parallel to the first surface of the device.
    Type: Application
    Filed: March 28, 2016
    Publication date: September 29, 2016
    Inventors: Margie RIOS, Aira Lourdes VILLAMOR, Maria Cristina ESTACIO, Armand Vincent JEREZA