Patents by Inventor Airell Richard Clark, II

Airell Richard Clark, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11109016
    Abstract: Various embodiments of the present technology may comprise methods and apparatus for error detection in an imaging system. The method and apparatus may comprise pixels arranged in rows and columns and an error detection circuit receiving pixel data generated by the pixels. The error detection circuit may detect errors and generate an error condition and/or signal, for example if one or more image frames are the same and/or a readout error has occurred.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: August 31, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Airell Richard Clark, II, Dwight Poplin
  • Patent number: 10438332
    Abstract: Various embodiments of the present technology may comprise a method and apparatus for pixel readout. The method and apparatus may comprise a pixel array capable of reading out one or more non-rectilinear subsets of the pixel array to form a non-rectilinear primary image. The one or more non-rectilinear subsets may be selected according to a desired rectilinear output image, wherein the rectilinear output image is formed using only the one or more subsets. The primary image may then be transformed to form the rectilinear output image.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: October 8, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Airell Richard Clark, II, Timothy Brown, Ignacio J. Perez, Agustin B. Hernandez
  • Publication number: 20180336667
    Abstract: Various embodiments of the present technology may comprise a method and apparatus for pixel readout. The method and apparatus may comprise a pixel array capable of reading out one or more non-rectilinear subsets of the pixel array to form a non-rectilinear primary image. The one or more non-rectilinear subsets may be selected according to a desired rectilinear output image, wherein the rectilinear output image is formed using only the one or more subsets. The primary image may then be transformed to form the rectilinear output image.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 22, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Airell Richard CLARK, II, Timothy BROWN, Ignacio J. PEREZ, Agustin B. HERNANDEZ
  • Publication number: 20170272740
    Abstract: Various embodiments of the present technology may comprise methods and apparatus for error detection in an imaging system. The method and apparatus may comprise pixels arranged in rows and columns and an error detection circuit receiving pixel data generated by the pixels. The error detection circuit may detect errors and generate an error condition and/or signal, for example if one or more image frames are the same and/or a readout error has occurred.
    Type: Application
    Filed: September 12, 2016
    Publication date: September 21, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Airell Richard CLARK, II, Dwight POPLIN
  • Patent number: 7714892
    Abstract: Disclosed are various systems, devices and methods for digital camera image stabilization. In one embodiment, a digital camera captures a plurality of digital images of a subject simultaneously or near-simultaneously and stores the captured images in memory as individual digital data sets. While the digital images are being captured simultaneously or near-simultaneously by means of a plurality of rolling shutters, a relative position determination device such as an angular rate sensor is employed to sense and save to memory data representative of the relative positions of the digital camera at the moments the individual digital images or frames are being exposed. Spatial shift directions and magnitudes are calculated in a processor of the camera on the basis of such data, and then applied to the individual data sets to form aligned data sets comprising aligned data points.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: May 11, 2010
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Airell Richard Clark, II, Richard Wesley Garvin, Donald Montgomery Reid
  • Patent number: 6822481
    Abstract: A clock gating circuit reduces the power dissipation in a digital circuit including at least one functional block by gating the clock signal at an input to a clock tree feeding the functional block. The clock gating circuit includes a logic gate that receives a clock signal and a clock disable signal generated by the functional block, and gates the clock signal at the input to the clock tree feeding the functional block. Further, a global signal generator is provided to transmit a global signal to each of the functional blocks to prevent the generation of clock disable signals, when necessary, such as during testing of chips.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: November 23, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Vamsi K. Srikantam, Airell Richard Clark, II