Patents by Inventor Aiswarya M. Pious

Aiswarya M. Pious has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12167530
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to EMI shielding and thermal conduction without using any surface area of a PCB. Embodiments of the EMI shield may include a planar top, with one or more walls extending from the planar top to a bottom surface of the PCB, the PCB having a top surface disposed between the bottom surface of the PCB and the planar top. A ground of the PCB may electrically couple with the one or more walls. The bottom of the walls may couple with an EMI gasket applied to a bottom chassis to increase the volume of EMI shielding. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: December 10, 2024
    Assignee: Intel Corporation
    Inventors: Jaejin Lee, James Panakkal, Min Suet Lim, Aiswarya M. Pious
  • Publication number: 20240406622
    Abstract: A computer-implemented method of audio processing comprises receiving, by at least one processor, multiple audio signals from multiple microphones. The audio signals are associated with audio emitted from a same source. The method also may include determining an audio quality indicator of individual ones of the audio signals using a neural network, and selecting at least one of the audio signals depending on the audio quality indicators.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: Jaison Fernandez, Adam Kupryjanow, Srikanth Potluri, Tarakesava Reddy Koki, Aiswarya M. Pious
  • Publication number: 20240334715
    Abstract: Technologies for memory on package with reduced package thickness are disclosed. In the illustrative embodiment, a die assembly includes a substrate with a processor die mounted on the top surface and a memory die mounted on the bottom surface. The die assembly is mounted on another substrate, such as a mainboard. A cavity is defined in the mainboard, and the memory die mounted on the bottom surface of the die assembly is positioned in the cavity. Positioning the memory die on the bottom surface of the die assembly can reduce the overall thickness of the die assembly and, therefore, can reduce the overall thickness of a device that incorporates the die assembly.
    Type: Application
    Filed: March 27, 2023
    Publication date: October 3, 2024
    Applicant: Intel Corporation
    Inventors: Navneet Kumar Singh, Phani Alaparthi, Samarth Alva, Ritu Bawa, Gaurav Hada, Aiswarya M. Pious
  • Patent number: 12106818
    Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 1, 2024
    Assignee: Intel Corporation
    Inventors: Aiswarya M. Pious, Raji James, Phani K. Alaparthi, George Vergis, Bill Nale, Konika Ganguly
  • Publication number: 20240129149
    Abstract: An example apparatus disclosed herein is to receive network data communicated via a first channel associated with the online collaboration session, the network data including received media data packets. The disclosed example apparatus is also to analyze the network data to determine first loopback data, the first loopback data including at least one of a first quality score based on a first analysis of the received media data packets or a second quality score based on a second analysis of media decoded from the received media data packets. The disclosed example apparatus is also to analyze local data obtained by a local client during the online collaboration session to determine second loopback data. The disclosed example apparatus is further to cause transmission of a loopback message to a moderator client via the second channel, the loopback message based on the first loopback data and the second loopback data.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Aiswarya M. Pious, Tao Tao, Stanley Jacob Baran, Michael Daniel Rosenzweig, Chia-Hung Sophia Kuo, Rahul R, Nagalakshmi S, Praveen Kashyap Ananta Bhat, Balvinder Pal Singh, Navya P, Jason Tanner, Passant V. Karunaratne, Venkateshan Udhayan, Srikanth Potluri
  • Publication number: 20220123776
    Abstract: Particular embodiments described herein provide for a tablet computer that can be configured to include a display, an antenna, a plurality of capacitance-based proximity sensors, and a configuration engine. The configuration engine uses the capacitance-based proximity sensors to determine a configuration of the tablet computer when the tablet computer is attached to an accessory. The capacitance-based proximity sensors can be specific absorption rate (SAR) proximity sensors used to determine when to reduce radiation from one or more antenna when the tablet computer is not coupled to the accessory and to determine a configuration of the tablet computer when the tablet computer is coupled to an accessory.
    Type: Application
    Filed: December 24, 2021
    Publication date: April 21, 2022
    Inventors: Tarakesava Reddy Koki, Mallari Hanchate, Aiswarya M. Pious, Vinay Kumar Chandrasekhara, Antonio Shiu Kee Cheng
  • Publication number: 20220095456
    Abstract: In one embodiment, a printed circuit board includes a first circuit board portion comprising a set of first conducting layers and one or more plated through hole (PTH) vias formed through the first conducting layers and a second circuit board portion comprising a set of second conducting layers. The second circuit board portion has an area less than an area of the first circuit board portion, and the second circuit board portion is coupled to the first circuit board portion via a laminate layer such that the first and second conducting layers are parallel with one another. The printed circuit board further includes one or more PTH vias formed through the first and second conducting layers in an area of the printed circuit board where the first and second circuit board portions overlap.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Arumanayagam Rajasekar, Tin Poay Chuah, Sushil Padmanabhan, Aiswarya M. Pious, Navneet Kumar Singh
  • Publication number: 20220077609
    Abstract: A connector to connect an electronic module to an edge of a first electronic circuit board is described. The module has a second electronic circuit board. The connector has a top part that houses a first row of I/Os. The top part is to be placed on a surface of the first electronic circuit board. The connector has a bottom part that houses a second row of I/Os. The bottom part is to be placed on an opposite surface of the first electronic circuit board, wherein, the top and bottom parts form inner and outer stand-offs when mater together. The inner stand-off is to reside within a through hole of the first electronic circuit board. The outer stand-off is to reside within free space off the edge of the first electronic circuit board. The second electronic circuit board is to be pressed in between the first row of I/Os and the second row of I/Os when the module is connected to the connector.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 10, 2022
    Inventors: Navneet Kumar SINGH, Aiswarya M. PIOUS, Richard S. PERRY, Amarjeet KUMAR, Siva Prasad JANGILI GANGA, Gaurav HADA, Sushil PADMANABHAN, Konika GANGULY
  • Publication number: 20210350952
    Abstract: An air mover external to a mobile computing device provides enhanced cooling to the device by generating forced air delivered to the device via cooling channels connected to openings in the device chassis. If the mobile computing device is passively cooled (is a fanless device), the enhanced cooling can enable the device or device components to operate at a higher power consumption level without exceeding device/component thermal limits or for features that consume high amounts of power (e.g., fast charging) to be incorporated into the device. The air mover can be integrated into or attached to a cable that provides power to the mobile computing device. The air mover can be powered by the cable. The air mover can dynamically adjust the flow rate of the forced air based on device/component performance information (temperature, power consumption, current consumption) or operational state information of the device.
    Type: Application
    Filed: July 20, 2021
    Publication date: November 11, 2021
    Inventors: Navneet Kumar Singh, Samarth Alva, Raghavendra S. Kanivihalli, Aiswarya M. Pious, Samantha Rao, Bijendra Singh
  • Publication number: 20210153340
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to EMI shielding and thermal conduction without using any surface area of a PCB. Embodiments of the EMI shield may include a planar top, with one or more walls extending from the planar top to a bottom surface of the PCB, the PCB having a top surface disposed between the bottom surface of the PCB and the planar top. A ground of the PCB may electrically couple with the one or more walls. The bottom of the walls may couple with an EMI gasket applied to a bottom chassis to increase the volume of EMI shielding. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 18, 2020
    Publication date: May 20, 2021
    Inventors: Jaejin Lee, James Panakkal, Min Suet Lim, Aiswarya M. Pious
  • Publication number: 20210151083
    Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.
    Type: Application
    Filed: December 23, 2020
    Publication date: May 20, 2021
    Inventors: Aiswarya M. PIOUS, Raji JAMES, Phani K. ALAPARTHI, George VERGIS, Bill NALE, Konika GANGULY
  • Publication number: 20190052111
    Abstract: System and techniques for wireless charging of a portable virtual reality (VR) host system are described herein. The present subject matter provides various examples to power a portable VR host system that allows for free movement by the user. In various embodiments the present subject matter provides connections on the footwear of the user that supply electrical power to a VR host worn by the user. In various examples, a connection technology is employed to provide connections between the user wearing the VR host system and conductive mats, plates, or flooring that are powered to provide electrical power to the VR host system via connections to the user's apparel when standing. Other forms of connection technology may be employed, such as inductive wireless technology or radio frequency signal technology that uses wireless power coils or antennae to receive power and provide it to the VR host worn by the user.
    Type: Application
    Filed: November 16, 2016
    Publication date: February 14, 2019
    Applicant: Intel Corporation
    Inventors: Jr-Wei Wu, Chetan Verma, Aiswarya M. Pious