Abstract: The present disclosure provides an off-chip memory address scrambling apparatus and method for a system on chip. The apparatus includes a true random number generator, a key memory and an on-chip security controller. The on-chip security controller is connected to the true random number generator, the key memory and an off-chip memory respectively and is configured to read or write data in the off-chip memory and perform address scrambling processing on the data.

Abstract: Embodiments of the disclosure provide a method and apparatus for encrypting and decrypting data. The method for encrypting data in a computer system can include: receiving, by a memory operation module, a first data and a second data for encryption; determining at least one storage area for a first encrypted data corresponding to the first data and a second encrypted data corresponding to the second data; generating at least one key based on the first and second data and the at least one storage area; and encrypting the first data and the second data using the at least one key to generate the first encrypted data and the second encrypted, respectively.

Abstract: Provided is a bitwise writing apparatus for a SOC system. The apparatus includes a slave device interface module, a decoding module and a master device interface module. The slave device interface module is configured to receive a write request sent by a master device interface of a bus controller and send the write request to the decoding module. The decoding module is configured to receive the write request sent by the slave device interface module, decode the write request and send valid information after the decoding to the master device interface module. The master device interface module is configured to receive the valid information sent by the decoding module, read data in a destination address, perform a bitwise operation for the read data to obtain new data, send a write request to a slave device interface of the bus controller and write the obtained new data into a peripheral register corresponding to the destination address.

Abstract: The present disclosure provides an off-chip memory address scrambling apparatus and method for a system on chip. The apparatus includes a true random number generator, a key memory and an on-chip security controller. The on-chip security controller is connected to the true random number generator, the key memory and an off-chip memory respectively and is configured to read or write data in the off-chip memory and perform address scrambling processing on the data.

Abstract: Provided is a bitwise writing apparatus for a SOC system. The apparatus includes a slave device interface module, a decoding module and a master device interface module. The slave device interface module is configured to receive a write request sent by a master device interface of a bus controller and send the write request to the decoding module. The decoding module is configured to receive the write request sent by the slave device interface module, decode the write request and send valid information after the decoding to the master device interface module. The master device interface module is configured to receive the valid information sent by the decoding module, read data in a destination address, perform a bitwise operation for the read data to obtain new data, send a write request to a slave device interface of the bus controller and write the obtained new data into a peripheral register corresponding to the destination address.

Abstract: Embodiments of the disclosure provide a method and apparatus for encrypting and decrypting data. The method for encrypting data in a computer system can include: receiving, by a memory operation module, a first data and a second data for encryption; determining at least one storage area for a first encrypted data corresponding to the first data and a second encrypted data corresponding to the second data; generating at least one key based on the first and second data and the at least one storage area; and encrypting the first data and the second data using the at least one key to generate the first encrypted data and the second encrypted, respectively.