Patents by Inventor Aiza Marie Agudon
Aiza Marie Agudon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12159820Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.Type: GrantFiled: December 31, 2020Date of Patent: December 3, 2024Assignee: STMicroelectronics, Inc.Inventors: Rennier Rodriguez, Aiza Marie Agudon, Maiden Grace Maming
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Patent number: 12074100Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.Type: GrantFiled: December 22, 2020Date of Patent: August 27, 2024Assignee: STMicroelectronics, Inc.Inventors: Rennier Rodriguez, Aiza Marie Agudon, Maiden Grace Maming
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Patent number: 11552007Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.Type: GrantFiled: February 25, 2021Date of Patent: January 10, 2023Assignee: STMicroelectronics, Inc.Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
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Publication number: 20210183750Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.Type: ApplicationFiled: February 25, 2021Publication date: June 17, 2021Applicant: STMicroelectronics, Inc.Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Jefferson TALLEDO, Moonlord MANALO, Ela Mia CADAG, Rammil SEGUIDO
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Publication number: 20210151368Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.Type: ApplicationFiled: December 31, 2020Publication date: May 20, 2021Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Maiden Grace MAMING
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Publication number: 20210111109Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.Type: ApplicationFiled: December 22, 2020Publication date: April 15, 2021Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Maiden Grace MAMING
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Patent number: 10957634Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.Type: GrantFiled: February 25, 2020Date of Patent: March 23, 2021Assignee: STMICROELECTRONICS, INC.Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
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Patent number: 10892212Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.Type: GrantFiled: November 9, 2017Date of Patent: January 12, 2021Assignee: STMICROELECTRONICS, INC.Inventors: Rennier Rodriguez, Aiza Marie Agudon, Maiden Grace Maming
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Publication number: 20200194355Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Jefferson TALLEDO, Moonlord MANALO, Ela Mia CADAG, Rammil SEGUIDO
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Patent number: 10615104Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.Type: GrantFiled: October 8, 2018Date of Patent: April 7, 2020Assignee: STMicroelectronics, Inc.Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
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Patent number: 10535588Abstract: The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.Type: GrantFiled: January 18, 2017Date of Patent: January 14, 2020Assignee: STMicroelectronics, Inc.Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo
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Publication number: 20190139875Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.Type: ApplicationFiled: November 9, 2017Publication date: May 9, 2019Inventors: Rennier Rodriguez, Aiza Marie Agudon, Maiden Grace Maming
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Publication number: 20190043790Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.Type: ApplicationFiled: October 8, 2018Publication date: February 7, 2019Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
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Patent number: 10109563Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.Type: GrantFiled: January 5, 2017Date of Patent: October 23, 2018Assignee: STMICROELECTRONICS, INC.Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
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Publication number: 20180204786Abstract: The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.Type: ApplicationFiled: January 18, 2017Publication date: July 19, 2018Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Jefferson TALLEDO
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Publication number: 20180190576Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.Type: ApplicationFiled: January 5, 2017Publication date: July 5, 2018Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
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Publication number: 20170263566Abstract: A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common encapsulating material, and cutting through the common encapsulating material between adjacent IC dies to define spaced apart IC packages carried by the substrate. An electrically conductive layer is positioned over the spaced apart IC packages and fills spaces between adjacent IC packages. The method further includes cutting through the electrically conductive layer between adjacent IC packages and through the substrate to form the shielded IC packages.Type: ApplicationFiled: March 14, 2016Publication date: September 14, 2017Inventors: Rennier RODRIGUEZ, Frederick ARELLANO, Aiza Marie AGUDON
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Patent number: 9761538Abstract: A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common encapsulating material, and cutting through the common encapsulating material between adjacent IC dies to define spaced apart IC packages carried by the substrate. An electrically conductive layer is positioned over the spaced apart IC packages and fills spaces between adjacent IC packages. The method further includes cutting through the electrically conductive layer between adjacent IC packages and through the substrate to form the shielded IC packages.Type: GrantFiled: March 14, 2016Date of Patent: September 12, 2017Assignee: STMICROELECTRONICS, INC.Inventors: Rennier Rodriguez, Frederick Arellano, Aiza Marie Agudon
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Publication number: 20170084490Abstract: A method is for making an integrated circuit (IC) device. The method may include dicing a wafer into IC dies, each IC die having an active surface, a back surface opposite the active surface, and a sidewall with a step defining a smaller periphery adjacent the back surface and a larger periphery adjacent the active surface. The method may include positioning a resin material between the back surface of each IC die and a respective substrate, and around each IC die so that the resin material abuts and is retained by the step.Type: ApplicationFiled: September 18, 2015Publication date: March 23, 2017Inventors: Bryan Christian Bacquian, Frederick Arellano, Aiza Marie Agudon