Patents by Inventor Aiza Marie Agudon

Aiza Marie Agudon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11552007
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: January 10, 2023
    Assignee: STMicroelectronics, Inc.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Publication number: 20210183750
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Application
    Filed: February 25, 2021
    Publication date: June 17, 2021
    Applicant: STMicroelectronics, Inc.
    Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Jefferson TALLEDO, Moonlord MANALO, Ela Mia CADAG, Rammil SEGUIDO
  • Publication number: 20210151368
    Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.
    Type: Application
    Filed: December 31, 2020
    Publication date: May 20, 2021
    Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Maiden Grace MAMING
  • Publication number: 20210111109
    Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Maiden Grace MAMING
  • Patent number: 10957634
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: March 23, 2021
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Patent number: 10892212
    Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: January 12, 2021
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Maiden Grace Maming
  • Publication number: 20200194355
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Jefferson TALLEDO, Moonlord MANALO, Ela Mia CADAG, Rammil SEGUIDO
  • Patent number: 10615104
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: April 7, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Patent number: 10535588
    Abstract: The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo
  • Publication number: 20190139875
    Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Maiden Grace Maming
  • Publication number: 20190043790
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 7, 2019
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Patent number: 10109563
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 23, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Publication number: 20180204786
    Abstract: The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 19, 2018
    Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Jefferson TALLEDO
  • Publication number: 20180190576
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Application
    Filed: January 5, 2017
    Publication date: July 5, 2018
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Publication number: 20170263566
    Abstract: A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common encapsulating material, and cutting through the common encapsulating material between adjacent IC dies to define spaced apart IC packages carried by the substrate. An electrically conductive layer is positioned over the spaced apart IC packages and fills spaces between adjacent IC packages. The method further includes cutting through the electrically conductive layer between adjacent IC packages and through the substrate to form the shielded IC packages.
    Type: Application
    Filed: March 14, 2016
    Publication date: September 14, 2017
    Inventors: Rennier RODRIGUEZ, Frederick ARELLANO, Aiza Marie AGUDON
  • Patent number: 9761538
    Abstract: A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common encapsulating material, and cutting through the common encapsulating material between adjacent IC dies to define spaced apart IC packages carried by the substrate. An electrically conductive layer is positioned over the spaced apart IC packages and fills spaces between adjacent IC packages. The method further includes cutting through the electrically conductive layer between adjacent IC packages and through the substrate to form the shielded IC packages.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: September 12, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Frederick Arellano, Aiza Marie Agudon
  • Publication number: 20170084490
    Abstract: A method is for making an integrated circuit (IC) device. The method may include dicing a wafer into IC dies, each IC die having an active surface, a back surface opposite the active surface, and a sidewall with a step defining a smaller periphery adjacent the back surface and a larger periphery adjacent the active surface. The method may include positioning a resin material between the back surface of each IC die and a respective substrate, and around each IC die so that the resin material abuts and is retained by the step.
    Type: Application
    Filed: September 18, 2015
    Publication date: March 23, 2017
    Inventors: Bryan Christian Bacquian, Frederick Arellano, Aiza Marie Agudon