Abstract: A flexible cross-connect with a data plane is presented which allows the establishment of connections between network interfaces at any network interface card to another network interface on any other network interface card. The system can cross-connect connections at an STS-1 and VT 1.5 granularity, and allows the switching and routing of information in a data plane without the use of the cross connect fabric. This permits routing, bridging, and concentration of data services to be performed without burdening of the cross connect. For reliability, a range of protection configurations can be employed including 1:1, 1:5 and mixed 1:N protection. A backplane is used which provides point-to-point traces between each card and the cross connect unit, between each card and a timing, communications and control unit, and between the network interface cards themselves.

Abstract: A flexible cross-connect with a data plane is presented which allows the establishment of connections between network interfaces at any network interface card to another network interface on any other network interface card. The system can cross-connect connections at an STS-1 and VT 1.5 granularity, and allows the switching and routing of information in a data plane without the use of the cross connect fabric. This permits routing, bridging, and concentration of data services to be performed without burdening of the cross connect. For reliability, a range of protection configurations can be employed including 1:1, 1:5 and mixed 1:N protection. A backplane is used which provides point-to-point traces between each card and the cross connect unit, between each card and a timing, communications and control unit, and between the network interface cards themselves.

Abstract: A flexible cross-connect with a data plane is presented which allows the establishment of connections between network interfaces at any network interface card to another network interface on any other network interface card. The system can cross-connect connections at an STS-1 and VT 1.5 granularity, and allows the switching and routing of information in a data plane without the use of the cross connect fabric. This permits routing, bridging, and concentration of data services to be performed without burdening of the cross connect. For reliability, a range of protection configurations can be employed including 1:1, 1:5 and mixed 1:N protection. A backplane is used which provides point-to-point traces between each card and the cross connect unit, between each card and a timing, communications and control unit, and between the network interface cards themselves.

Abstract: A time slot interchanger (10) includes a D-channel processing device (30). The D-channel processing device (30) includes a main memory (32), a D-channel memory (34), and a D-channel assembler (36). The main memory (32) receives telephony data and signaling traffic from a subscriber in the form of integrated services digital network signals. Two-bit D-channel signaling portions of each integrated services digital network signals are extracted and placed into the D-channel memory (34). The D-channel assembler (36) assembles the two-bit D-channel signaling portions into eight-bit digital signal level zero (DS0) signals. The eight-bit DS0 signals are stored in the D-channel memory (34) for subsequent transfer with selected telephony data traffic from the main memory (32) over a synchronous optical network link.

Abstract: The present invention describes a robust register circuit for protecting critical control points in data transmission and telecommunications equipment against software included failures. A circuit is provided wherein duplicated data words are written into a pair of registers of any desired bit length. A digital comparator determines whether the two data words are the same, and initiates a data transfer into a third register for transmission to critical hardware control points only when two identical sequential data words are recognized. When no such recognition occurs, new data is not transferred to the third register, and the hardware control points remain controlled by the previous data in the third register.