Abstract: Techniques are described for semiconductor chips with reduced capacitive power dissipation as a result of improved conductor line spacing. The approaches are particularly applicable to 0.25 micron chip design processes and below. According to one aspect, where there are n available metallization layers available to the designer, a smaller number of layers, such as n−1, are utilized initially in developing a routing design. Then, at least one further metallization layer is used to systematically route conductors, such as bus conductors, to increase the number of metal pitches between conductors, by promoting conductors from one layer to another.

Abstract: Techniques are described for semiconductor chips with reduced capacitive power dissipation as a result of improved conductor line spacing. The approaches are particularly applicable to 0.25 micron chip design processes and below. According to one aspect, where there are n available metallization layers available to the designer, a smaller number of layers, such as n-1, are utilized initially in developing a routing design. Then, at least one further metallization layer is used to systematically route conductors, such as bus conductors, to increase the number of metal pitches between conductors, by promoting conductors from one layer to another.

Abstract: A memory cell (i.e. CMMC) for use in GaAs circuits such as MESFETs wherein read and write operations can both be performed using as few as two access transistors biased as current mirrors to driver transistors of the cell. This new memory cell offers larger read access currents for faster access times and also faster write times than in a conventional memory cell. This cell does not require that the driver transistors be scaled with respect to the access transistors, resulting in a smaller cell area. In the CMMC, the gate of each access transistor is biased by a storage node voltage. The source node of each access transistor is biased by a word line which is pulled low, towards ground. As a result, each access transistor has a gate-source voltage ofV.sub.GS (access)=V.sub.CS +V.sub.CG -V.sub.WORDwhere V.sub.CS is the cell storage voltage (with respect to cell ground), V.sub.CG is the cell ground voltage and V.sub.WORD is the word line voltage at the cell.