Patents by Inventor Ajay D. Kamdar

Ajay D. Kamdar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for constraining the compaction of components of a circuit layout
    Patent number: 5636132
    Abstract: Integrated circuit design method and apparatus with user defined constraints for constraining compaction of an integrated circuit layout. Logical boundary constraints allow a user to move layout designs to different process technologies without concern that device size changes will disrupt the layout. Multiple grid constraints allow a user to set grids of different sizes for the same or different circuit layers in a design. And pre-compaction constraints may be imposed by a user to preserve components' relationships in an initial topology throughout the compaction process.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: June 3, 1997
    Assignee: Mentor Graphics Corporation
    Inventor: Ajay D. Kamdar