Abstract: A memory device includes a memory array, a memory controller, data lines connecting the memory array and the memory controller, and a delay compensation module. The delay compensation module includes a delay line that provides delayed clock signals, a look-up table that stores a mapping between predefined data bit patterns and corresponding propagation delays for each data line, and delay compensation logic modules corresponding to the data lines. The delay compensation logic modules receive data bit patterns carried by the data lines, select propagation delays based on the data bit patterns and the look-up table data, and delay the bits carried by corresponding ones of the data lines based on delayed clock signals corresponding to the propagation delays.