Abstract: According to an aspect, a computer-implemented method includes intercepting a call to invoke execution of a service as part of performing a synchronous transaction. A current state of the synchronous transaction is captured and persisted in a transaction object corresponding to the synchronous transaction. Execution of the service is invoked.

Abstract: Techniques are disclosed relating to a processor load-store unit. In some embodiments, the load-store unit is configured to execute load/store instructions in parallel using first and second pipelines and first and second tag memory arrays. In tag write conflict situations, the load-store unit may arbitrate between the first and second pipelines to ensure the first and second tag memory array contents remain identical. In some embodiments, a data cache tag replay scheme is utilized. In some embodiments, executing load/store instructions in parallel with fills, probes, and store-updates, using separate but identical tag memory arrays, may advantageously improve performance.

Abstract: An approach for an automated task management system to accomplish set goals by completing a predefined set of tasks for that goal is disclosed. The approach includes creating a goal object by one or more users and creating one or more task objects associated with the goal object by the one or more users. The approach includes executing a first task of the one or more task objects and determining if there is one or more deviations associated with executing the first task. Users can directly define deviations which are stored into the tasks directly as a deviation path without needing admin approval. Based on determining there is the one or more deviations, the approach can optionally ask for an approval from an administrator. Deviation tasks objects are stored into the goal object for future users to view and use.

Abstract: An approach for an automated task management system to accomplish set goals by completing a predefined set of tasks for that goal is disclosed. The approach includes creating a goal object by one or more users and creating one or more task objects associated with the goal object by the one or more users. The approach includes executing a first task of the one or more task objects and determining if there is one or more deviations associated with executing the first task. Users can directly define deviations which are stored into the tasks directly as a deviation path without needing admin approval. Based on determining there is the one or more deviations, the approach can optionally ask for an approval from an administrator. Deviation tasks objects are stored into the goal object for future users to view and use.

Abstract: A computer-implemented method includes: receiving, by a computer device, input to tag at least one line of code with one of plural predefined types of metadata tags, wherein the at least one line of code is a subset of a source code that is stored in a code repository and editable by plural different users via a client source code editor program; tagging, by the computer device, the at least one line of code with the one of the plural predefined types of metadata tags; detecting, by the computer device, a change to the at least one line of code after the tagging; and generating, by the computer device, an alert based on the detecting the change to the at least one line of code.

Abstract: Computer-implemented methods, systems, and computer program products are disclosed in which a first computing device sends a meeting request for person(s) to a second computing device. The first computing device receives from the second computing device, first token(s) granting limited access to calendar information for the person(s) sufficient for conflict clearance, the token(s) having restriction(s). The restriction(s) include one or more of a lifespan for the limited access, an identification of which calendar entries are accessible, an indication of how much of a calendar entry is accessible, a use count for the limited access, showing only available time and encryption of the calendar information. The first computing device sends to the second computing device, a meeting invitation for the person(s) based on the limited access. The first computing device then receives from the second computing device, an acceptance for the meeting invitation.

Abstract: A computer-implemented method includes: receiving, by a computer device, input to tag at least one line of code with one of plural predefined types of metadata tags, wherein the at least one line of code is a subset of a source code that is stored in a code repository and editable by plural different users via a client source code editor program; tagging, by the computer device, the at least one line of code with the one of the plural predefined types of metadata tags; detecting, by the computer device, a change to the at least one line of code after the tagging; and generating, by the computer device, an alert based on the detecting the change to the at least one line of code.

Abstract: Disclosed are methods and apparatus for bit packing data having various bit widths in a computer system. The methods and apparatus utilize a fixed bit packing or unpacking network that is configured to pack or unpack data bits of a number of different bit widths from a first number of bit locations to a second number of bit locations in the computer system. The network is specifically configured to pack bits stored in a same bit slot position in respective bit locations of the first number of bit locations by routing the bits into bit slots of a same bit location in the second number of bit locations to form bit bundles in respective ones of the second number of bit locations. Use of a fixed packing network affords optimal matching of bit width to an application that minimizes cost, area, and power, as well as decreasing or minimizing latency.

Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.

Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified, in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.

Abstract: In a particular embodiment, a very long instruction word (VLIW) processor is operable to execute VLIW instructions. At least one of the VLIW instructions includes a first load or store instruction and a second load or store instruction. The first instruction and the second instruction are executed as a single atomic unit. At least one of the first and second instructions is a store-conditional instruction.

Abstract: A multi-stage multiplexing operation that includes combined selection and data alignment or data replication is disclosed. In a particular embodiment, a method includes performing a first stage of a multi-stage multiplexing operation. During the first stage, a first data source is selected from a first plurality of data sources. At least one of a first data alignment operation and a first data replication operation is also performed on first data from the selected first data source during the first stage.

Abstract: In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a control logic circuit adapted to identify a partition replacement policy associated with the identified one of the at least two partitions based on a partition indicator. The control logic circuit controls replacement of data within the cache according to the identified partition replacement policy in response to a cache miss event.

Abstract: In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a control logic circuit adapted to identify a partition replacement policy associated with the identified one of the at least two partitions based on a partition indicator. The control logic circuit controls replacement of data within the cache according to the identified partition replacement policy in response to a cache miss event.

Abstract: An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.

Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines.