Patents by Inventor Ajay J. Joshi

Ajay J. Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250097009
    Abstract: An FPGA-based accelerator for bootstrappable fully homomorphic encryption (FHE) employs (1) acceleration of scalar arithmetic operations using a multi-word approach for efficient utilization of standard-width components (multipliers/adders) on custom-width operands; (2) a performant, shift-based modular reduction technique that avoids the need for expensive multipliers; (3) an improved datapath for an expensive Key Switch operation; and (4) an efficient organization of on-chip memory for storing custom-width operands and supplying them at high bandwidth to computation units.
    Type: Application
    Filed: December 2, 2024
    Publication date: March 20, 2025
    Inventors: Rashmi S. Agrawal, Ajay J. Joshi
  • Patent number: 12200101
    Abstract: An FPGA-based accelerator for bootstrappable fully homomorphic encryption (FHE) employs (1) acceleration of scalar arithmetic operations using a multi-word approach for efficient utilization of standard-width components (multipliers/adders) on custom-width operands; (2) a performant, shift-based modular reduction technique that avoids the need for expensive multipliers; (3) an improved datapath for an expensive Key Switch operation; and (4) an efficient organization of on-chip memory for storing custom-width operands and supplying them at high bandwidth to computation units.
    Type: Grant
    Filed: June 13, 2024
    Date of Patent: January 14, 2025
    Assignee: Trustees of Boston University
    Inventors: Rashmi S. Agrawal, Ajay J. Joshi
  • Publication number: 20240421971
    Abstract: An FPGA-based accelerator for bootstrappable fully homomorphic encryption (FHE) employs (1) acceleration of scalar arithmetic operations using a multi-word approach for efficient utilization of standard-width components (multipliers/adders) on custom-width operands; (2) a performant, shift-based modular reduction technique that avoids the need for expensive multipliers; (3) an improved datapath for an expensive Key Switch operation; and (4) an efficient organization of on-chip memory for storing custom-width operands and supplying them at high bandwidth to computation units.
    Type: Application
    Filed: June 13, 2024
    Publication date: December 19, 2024
    Inventors: Rashmi S. Agrawal, Ajay J. Joshi
  • Patent number: 8914712
    Abstract: A data processing device can perform error detection and correction in two stages: in the first stage, error detection is performed for the load data using the in-line error detection information. If a first type of error is detected in the data segment, the error is corrected using the in-line error detection information. If a second type of error is detected error correction is performed using the residual sum.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: December 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, Ajay J. Joshi, Bobak A. Nazer
  • Publication number: 20130227368
    Abstract: A data processing device can perform error detection and correction in two stages: in the first stage, error detection is performed for the load data using the in-line error detection information. If a first type of error is detected in the data segment, the error is corrected using the in-line error detection information. If a second type of error is detected error correction is performed using the residual sum.
    Type: Application
    Filed: February 27, 2012
    Publication date: August 29, 2013
    Applicants: BOSTON UNIVERSITY, FREESCALE SEMICONDUCTOR, INC.
    Inventors: Ravindraraj Ramaraju, Ajay J. Joshi, Bobak A. Nazer