Patents by Inventor Ajay Janardanan

Ajay Janardanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12323150
    Abstract: Embodiments herein relate to a circuit which generates a sawtooth waveform based on an adaptive feedback loop that self-corrects the ramp up rate to account for variations in a device. The sawtooth waveform is obtained by repeatedly charging and discharging a capacitor according to a clock signal. The sawtooth waveform can be sampled once per clock period at a comparator which provides a corresponding binary output to a state machine. If the binary output indicates the amplitude of the sawtooth waveform is below a desired maximum voltage, the state machine outputs a code word to a digitally-controlled variable current source to increase the output current. The sawtooth waveform can be used to provide a pulse-width modulated (PWM) waveform such as for a DC-DC converter.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: June 3, 2025
    Assignee: Intel Corporation
    Inventors: Juan Munoz Constantine, Christopher Schaef, Ajay Janardanan, Alexander Lyakhov
  • Publication number: 20220060180
    Abstract: Embodiments herein relate to a circuit which generates a sawtooth waveform based on an adaptive feedback loop that self-corrects the ramp up rate to account for variations in a device. The sawtooth waveform is obtained by repeatedly charging and discharging a capacitor according to a clock signal. The sawtooth waveform can be sampled once per clock period at a comparator which provides a corresponding binary output to a state machine. If the binary output indicates the amplitude of the sawtooth waveform is below a desired maximum voltage, the state machine outputs a code word to a digitally-controlled variable current source to increase the output current. The sawtooth waveform can be used to provide a pulse-width modulated (PWM) waveform such as for a DC-DC converter.
    Type: Application
    Filed: November 2, 2021
    Publication date: February 24, 2022
    Inventors: Juan Munoz Constantine, Christopher Schaef, Ajay Janardanan, Alexander Lyakhov
  • Patent number: 10050635
    Abstract: A device includes an amplifier and calibration circuitry coupled to the amplifier. The calibration circuitry is configured to receive calibration values. The calibration circuitry is also configured to generate an output value in response to receiving a timing input.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: August 14, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Burt Price, Ajay Janardanan, Yeshwant Kolla
  • Publication number: 20170338830
    Abstract: A device includes an amplifier and calibration circuitry coupled to the amplifier. The calibration circuitry is configured to receive calibration values. The calibration circuitry is also configured to generate an output value in response to receiving a timing input.
    Type: Application
    Filed: September 22, 2016
    Publication date: November 23, 2017
    Inventors: Burt Price, Ajay Janardanan, Yeshwant Kolla
  • Patent number: 9712126
    Abstract: Automatically calibrating operational amplifier (op-amp) systems for mitigating effects of offset voltages are disclosed. In one aspect, an automatically calibrating op-amp system is provided that employs an analog calibration signal corresponding to a calibration mode to compensate an output voltage signal of an op-amp corresponding to an amplify mode. An automatic calibration circuit is included that employs a successive approximation register (SAR) controller configured to successively generate digital values based on the output voltage signal of the op-amp in response to a mode signal indicating the calibration mode. The automatic calibration circuit includes a digital-to-analog converter (DAC) configured to convert each successive digital value into the analog calibration signal in response to the mode signal indicating the calibration mode. The analog calibration signal is provided to an auxiliary differential input of the op-amp to compensate for the composite offset voltage in the amplify mode.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: July 18, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Burt Lee Price, Yeshwant Nagaraj Kolla, Dhaval Rajeshbhai Shah, Ajay Janardanan
  • Publication number: 20170047903
    Abstract: Automatically calibrating operational amplifier (op-amp) systems for mitigating effects of offset voltages are disclosed. In one aspect, an automatically calibrating op-amp system is provided that employs an analog calibration signal corresponding to a calibration mode to compensate an output voltage signal of an op-amp corresponding to an amplify mode. An automatic calibration circuit is included that employs a successive approximation register (SAR) controller configured to successively generate digital values based on the output voltage signal of the op-amp in response to a mode signal indicating the calibration mode. The automatic calibration circuit includes a digital-to-analog converter (DAC) configured to convert each successive digital value into the analog calibration signal in response to the mode signal indicating the calibration mode. The analog calibration signal is provided to an auxiliary differential input of the op-amp to compensate for the composite offset voltage in the amplify mode.
    Type: Application
    Filed: March 30, 2016
    Publication date: February 16, 2017
    Inventors: Burt Lee Price, Yeshwant Nagaraj Kolla, Dhaval Rajeshbhai Shah, Ajay Janardanan