Abstract: Methods, systems, apparatus, and tangible non-transitory carrier media encoded with one or more computer programs that can determine the path or route most likely navigated by a mobile target are described. In accordance with particular embodiments, the most likely path or route is determined based on path-based scoring of position estimates obtained from different types of complementary locationing signal sources. Instead of fusing the position data derived from the different types of signal sources, these particular embodiments determine the most likely path navigated by the mobile target based on an independent aggregation of the position estimates derived from complementary signals of different source types.

Abstract: A low-cost, multi-function tracking system with a form factor that unobtrusively integrates the components needed to implement a combination of different localization techniques and also is able to perform a useful ancillary function that otherwise would have to be performed with the attendant need for additional materials, labor, and expense. An example tracking system is implemented as an adhesive product that integrates tracking components within a flexible adhesive structure in a way that not only provides a cost-effective platform for interconnecting, optimizing, and protecting the components of the tracking system but also maintains the flexibility needed to function as an adhesive product that can be deployed seamlessly and unobtrusively into various tracking applications and workflows, including person and object tracking applications, and asset management workflows such as manufacturing, storage, shipping, delivery, and other logistics associated with moving products and other physical objects.

Abstract: In accordance with one embodiment of the invention, a method and apparatus are provided for testing a wafer while the wafer is disposed in a wafer carrier. The test results can be utilized to adjust the manufacturing process and thereby increase processing yield.

Abstract: Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for partial wafer test; design for partial probing; partial IC probecards; partial IC test equipment; partial IC quality determinations; partial IC test optimization; and partial test optimization. Other aspects may also be included. Systems and methods incorporating these features to test partially completed three-dimensional ICs may result in saved time and effort, and less scraped material, as the partial device is not built any further when a bad partial device is detected. This results in lower costs and higher yield.

Abstract: Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for partial wafer test; design for partial probing; partial IC probecards; partial IC test equipment; partial IC quality determinations; partial IC test optimization; and partial test optimization. Other aspects may also be included. Systems and methods incorporating these features to test partially completed three-dimensional ICs may result in saved time and effort, and less scraped material, as the partial device is not built any further when a bad partial device is detected. This results in lower costs and higher yield.

Abstract: An excitation signal generator (“ESG”) is described. The ESG generates an minimized excitation signal for use in a test system to generate a functional model of a device under test (“DUT”) where extreme values of the minimized excitation signal are increased toward a central value without changing the power spectrum at the DUT.

Abstract: Creating a low-bandwidth channel in a high-bandwidth channel. By taking advantage of extra bandwidth in a high-bandwidth channel, a low-bandwidth channel is created by inserting extra packets. When an inter-packet gap of the proper duration is detected, the extra packet is inserted and any incoming packets on the high-bandwidth channel are stored in an elastic buffer. Observing inter-packet gaps, minimal latency is introduced in the high-bandwidth channel when there is no extra packet in the process of being sent, and the effects of sending a packet on the low-bandwidth channel are absorbed and distributed among other passing traffic.

Abstract: From a logic device comprising logic circuits and a built-in self-test system (BIST) comprising scan chains, diagnostic information is obtained by using the scan chains to apply a stimulus vector to the logic circuits, to capture responses of the logic circuits to the stimulus vector and to shift the captured responses towards the outputs of the scan chains; generating a representative signature representing the responses output by the scan chains; concurrently storing the responses output by the scan chains temporarily such no more than a most-recently output subset of the responses is stored; determining whether the representative signature is a fault-indicating representative signature; and, when the representative signature is a fault-indicating representative signature, outputting at least some of the stored responses. The output responses are usable as diagnostic information.

Abstract: An ATE system is described for testing one or more DFT testing blocks contained in one or more DUTs when coupled to the ATE system. The ATE system includes hardware resources and software processes under the control of a DPK (Distributed Processing Kernel). The DPK couples the hardware resources and software processes as needed for a first DFT testing block to be enabled for testing only when such resources and processes are available and locked for the first DFT testing block. The DPK is coupled to the first DFT testing blocks via data channels and control channels that are selected as needed for having the first DFT testing block enabled for testing. The channels are under the control of an DUTs-ATE interface which is directed by the DPK for connecting the first DFT testing block to the locked hardware resource and the locked software processes.

Abstract: An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit communicate with one another using an inter-processor communications controller associated with each re-configurable test processor. The communications include configuration information, control information, communication protocols, stimulus data, and responses. Configuration information and stimulus data can also be read from a memory. Configuration information is used to configure one or more re-configurable test processors. Once configured, the re-configurable test processor or processors process the data in order to generate one or more test signals. The one or more test signals are then used to test a DUT.

Abstract: A system and method electronically tests devices. The method comprises receiving a first testing model including a first plurality of parameters and acceptable limits for the first plurality of parameters; receiving a second testing model including a second plurality of parameters and acceptable limits for the second plurality of parameters; receiving a first value for a first parameter from the first plurality of parameters, the first parameter at least partially affecting a second parameter from the second plurality of parameters; determining a second value for the second parameter based on the first value; determining if the first value is within the acceptable limits for the first parameter; determining if the second value is within the acceptable limits for the second parameter; and providing an indication when at least one of the first and second values is outside the acceptable limits for a corresponding one of the first and second parameters.

Abstract: In accordance with one embodiment of the invention, a method and apparatus are provided for testing a wafer while the wafer is disposed in a wafer carrier. The test results can be utilized to adjust the manufacturing process and thereby increase processing yield.

Abstract: The model-based method tests compliance of production devices with the performance specifications of a device design. The production devices are manufactured in accordance with the device design by a manufacturing process. In the method, a simple model form based on the device design and the performance specifications is developed, a stimulus for testing the production devices is specified and each production device is tested. The model form has a basis function and model form parameters for the basis function. The model form parameters are dependent on the manufacturing process and differ in value among the production devices. A production device is tested by measuring the response of the production device to the stimulus; extracting, using the model form, the values of the model form parameters for the production device from the measured response and the stimulus; and checking compliance of the production device with the performance specifications using the extracted values of the model form parameters.

Abstract: Creating a low-bandwidth channel in a high-bandwidth channel. By taking advantage of extra bandwidth in a high-bandwidth channel, a low-bandwidth channel is created by inserting extra packets. When an inter-packet gap of the proper duration is detected, the extra packet is inserted and any incoming packets on the high-bandwidth channel are stored in an elastic buffer. Observing inter-packet gaps, minimal latency is introduced in the high-bandwidth channel when there is no extra packet in the process of being sent, and the effects of sending a packet on the low-bandwidth channel are absorbed and distributed among other passing traffic.

Abstract: A wafer test head and ATE for testing semiconductor wafers. The wafer test head having a plurality of sides that can each be used to test a different semiconductor wafer. The architecture of the wafer test head enables electrical connections to probe card located on two different sides of the wafer test head. Multiple silicon wafers can be tested for proper functionality at the same time or in an interleaved fashion via a single multi-sided wafer test head. The internal architecture of an exemplary wafer test head allows printed circuit cards to be able to electrically connected to multiple wafer test locations on a single wafer test head.

Abstract: An ATE system is described for testing one or more DFT testing blocks contained in one or more DUTs when coupled to the ATE system. The ATE system includes hardware resources and software processes under the control of a DPK (Distributed Processing Kernel). The DPK couples the hardware resources and software processes as needed for a first DFT testing block to be enabled for testing only when such resources and processes are available and locked for the first DFT testing block. The DPK is coupled to the first DFT testing blocks via data channels and control channels that are selected as needed for having the first DFT testing block enabled for testing. The channels are under the control of an DUTs-ATE interface which is directed by the DPK for connecting the first DFT testing block to the locked hardware resource and the locked software processes.

Abstract: From a logic device comprising logic circuits and a built-in self-test system (BIST) comprising scan chains, diagnostic information is obtained by using the scan chains to apply a stimulus vector to the logic circuits, to capture responses of the logic circuits to the stimulus vector and to shift the captured responses towards the outputs of the scan chains; generating a representative signature representing the responses output by the scan chains; concurrently storing the responses output by the scan chains temporarily such no more than a most-recently output subset of the responses is stored; determining whether the representative signature is a fault-indicating representative signature; and, when the representative signature is a fault-indicating representative signature, outputting at least some of the stored responses. The output responses are usable as diagnostic information.

Abstract: A wafer test head and ATE for testing semiconductor wafers. The wafer test head having a plurality of sides that can each be used to test a different semiconductor wafer. The architecture of the wafer test head enables electrical connections to probe card located on two different sides of the wafer test head. Multiple silicon wafers can be tested for proper functionality at the same time or in an interleaved fashion via a single multi-sided wafer test head. The internal architecture of an exemplary wafer test head allows printed circuit cards to be able to electrically connected to multiple wafer test locations on a single wafer test head.

Abstract: From a memory device comprising a memory circuit and a built-in self-test system (BIST), diagnostic information is deterministically obtained by using the BIST to perform a test sequence that tests the memory circuit. The test sequence comprises writing one or more test patterns at memory locations in the memory circuit and reading respective output patterns from the memory locations. Diagnostic patterns corresponding to the output patterns are losslessly compressed to generate compressed diagnostic information. The compressed diagnostic information is temporarily stored and, at one or more predetermined points in the test sequence, the compressed diagnostic information is output from the memory device under test.

Abstract: Creating a low-bandwidth channel in a high-bandwidth channel. By taking advantage of extra bandwidth in a high-bandwidth channel, a low-bandwidth channel is created by inserting extra packets. When an inter-packet gap of the proper duration is detected, the extra packet is inserted and any incoming packets on the high-bandwidth channel are stored in an elastic buffer. Observing inter-packet gaps, minimal latency is introduced in the high-bandwidth channel when there is no extra packet in the process of being sent, and the effects of sending a packet on the low-bandwidth channel are absorbed and distributed among other passing traffic.