Abstract: A system and method in which a plurality of dice on a semiconductor wafer are interconnected to enable efficient testing thereof. In certain embodiments a plurality of dice are interconnected in a manner that enables test data to be communicated from a tester system to a plurality of dice for concurrent testing of such plurality of dice. Depending on the amount of interconnection, all or a portion of each of the plurality of dice may be tested concurrently. In certain embodiments, a plurality of dice are interconnected in a manner that enables test data to be communicated from one die to at least one other die. In certain embodiments, a plurality of dice are interconnected in a manner that enables such dice to be tested concurrently while maintaining a repeatable pattern at the reticle level for fabricating such dice.

Abstract: A testing system and various methods involving testing of a device under test (DUT) use a device model to model a stimulus-response behavior of a the DUT. The testing system includes a device model of the DUT that is fitted to the stimulus-response behavior of the DUT and a measurement projector connected to an output of the device model. The device model includes a block diagram model and a difference model. Test metrics for the DUT are produced by the measurement projector from an output of the fitted device model.