Abstract: A test-circuit includes a PLL-divider outputting first and third clock-signals as PLL clock-signals during functional mode and a capture-phase of transition and stuck-at-modes, and outputting a second clock-signal based upon an external clock-signal as an ATE clock-signal during a shift-phase of the transition and stuck-at-mode. An OCC passes the clock-signals in functional mode, transition capture mode, and stuck-at capture mode through sub-paths within first paths within first and second clock selection circuits so the first and third clock-signals are passed through less than the entire first paths, the sub-paths being first and second functional clock paths.

Abstract: An apparatus has a large block of synchronous logic arranged to include a first partition and a second partition. The first partition is configured to receive a first clock signal during a functional mode and during a test mode. The second partition is configured to receive the first clock signal during the functional mode, and the second partition configured to receive a second clock signal during a test mode. The second clock signal has the same frequency as the first clock signal. The second clock signal has a different phase from the first clock signal.

Abstract: An apparatus has a large block of synchronous logic arranged to include a first partition and a second partition. The first partition is configured to receive a first clock signal during a functional mode and during a test mode. The second partition is configured to receive the first clock signal during the functional mode, and the second partition configured to receive a second clock signal during a test mode. The second clock signal has the same frequency as the first clock signal. The second clock signal has a different phase from the first clock signal.

Abstract: A first circuit has a reset input. A second circuit is configured to be reset and provide an output. A test circuit is configured to test the first circuit and second circuit. The test circuit is configured such that a fault with the first circuit and said second circuit is determined in dependence on an output of the first circuit.

Abstract: A first circuit has a reset input. A second circuit is configured to be reset and provide an output. A test circuit is configured to test the first circuit and second circuit. The test circuit is configured such that a fault with the first circuit and said second circuit is determined in dependence on an output of the first circuit.