Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors a frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust a frequency of the clock signal.

Abstract: Methods and systems for simulating a system model are provided. The method includes loading into a computing system the system model that includes a plurality of event generating device models and non-event generating device models, scheduling a next event for each of the event generating device models independent of the next event of each other of the device models, advancing time to an earliest of the scheduled next events that is scheduled at a host device, committing the earliest of the scheduled next events, and replacing the earliest of the scheduled next events with a new next event for the host device.