Patents by Inventor Ajay N. Bhoj

Ajay N. Bhoj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8767501
    Abstract: Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Ajay N. Bhoj
  • Publication number: 20140025881
    Abstract: Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajiv V. Joshi, Ajay N. Bhoj
  • Patent number: 8578316
    Abstract: A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.
    Type: Grant
    Filed: September 8, 2012
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Ajay N. Bhoj
  • Publication number: 20130275937
    Abstract: A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.
    Type: Application
    Filed: September 8, 2012
    Publication date: October 17, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajiv V. Joshi, Ajay N. Bhoj
  • Patent number: 8490244
    Abstract: A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Ajay N. Bhoj