Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller coupled to the processor cores. The node controller is configured to route communications from the processor cores to other devices in a computer system. The node controller comprises a circuit coupled to receive the communications from the processor cores. In a redundant execution mode in which at least a first processor core is redundantly executing code that a second processor core is also executing, the circuit is configured to compare communications from the first processor core to communications from the second processor core to verify correct execution of the code. In some embodiments, the processor cores and the node controller may be integrated onto a single integrated circuit chip as a CMP. A similar method is also contemplated.

Abstract: Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones generate the true and complement carry signals. Other embodiments comprising additional features, such as shared logic cone decomposition, are also provided.

Abstract: Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones generate the true and complement carry signals. Other embodiments comprising additional features, such as shared logic cone decomposition, are also provided.

Abstract: A method and apparatus for protecting dynamic logic circuits from the effects of noise at the inputs to the dynamic logic circuits is disclosed. Parallel current flow or evaluate paths which couple an output node through a common node to a low voltage or ground rail include extra transistors in the current flow or evaluate path to allow the inputs to be protected while maintaining the operation and integrity of the circuit.

Abstract: The apparatus and method of the present invention operates to perform a floating-point operation involving at least two operands in floating-point representation. The apparatus comprises two concurrent data paths, a short path and a long path. The short path is used to produce a result of the floating-point operation if the floating-point operation is a subtract operation and the exponent difference of the two operands is 0, or if the floating-point operation is a subtract operation, the exponent difference is 1, and the mantissa of the operand with a larger exponent is within a predetermined number range. The long path is used to produce a result of the floating-point operation if the floating point operation is an addition operation, or if it is a subtraction operation and the exponent difference is larger than one, or if it is a subtract operation, the exponent difference is 1, and the mantissa of the operand with the larger exponent is within another predetermined number range.

Abstract: A register array system including a first number of rows by a second number of columns of data registers, a read line, a read bit line, and a single pull down device corresponding to each data register in each column of data registers and configured to discharge, in response to being turned on, the read bit line corresponding to the column of data registers. The pull down device corresponding to a data register is only turned in response to a clock signal, a read enable signal, and the data stored in the data register each having a high value. Therefore, the capacitance associated with the read bit line corresponding to a column of data registers stays at the same capacitance value during the precharging phase and during a multi-hot condition. The problem of voltage droop caused by charging sharing in a multi-hot condition is thus eliminated.

Abstract: The present invention provides a register array system and a method for reading the register array system that essentially eliminate the problem of charge sharing in a multi-hot condition. The register array system comprises a first number of rows by a second number of columns of data registers, a read word line corresponding to each row of data registers, a read bit line corresponding to each column of data registers, and a single pull down device corresponding to each data register in each column of data registers and configured to discharge, in response to being turned on, the read bit line corresponding to the column of data registers. The pull down device corresponding to a data register is only turned in response to a clock signal, a read enable signal, and the data stored in the data register each having a high value.

Abstract: An FPU configured to operate in normal and fast modes. In normal mode, floating point instructions are stalled in an address calculation unit of the processor until the previously issued floating point instruction has cleared the FPU, thereby indicating that the previous floating point instruction will not have an exception. In fast mode, the address calculation unit will issue a next floating point instruction to the FPU, where it is held in a 4-deep instruction queue, regardless of whether a prior instruction has cleared. By eliminating stalls in the instruction execution pipeline caused by floating point instructions being held in the address calculation unit pending clearance of the prior floating point instruction, the instruction execution pipeline may issue floating point instructions to the FPU at a faster rate.

Abstract: Exponent conversion logic implements floating point exponent conversion of single/double precision to an extended format (IEEE 754 standard), such as in the floating point unit of an x86 processor. The SP (single precision)/DP (double precision) to EP (extended precision exponent conversion technique avoids using an adder (with the attendant propagation delay). For SP exponents (8 bit), the exponent conversion logic implements conversion to EP format (15 bits) as follows (FIG. 3a): (a) transferring the 7 LSB (least significant bits) of the SP exponent (41) as the corresponding 7 LSBs of the EP format (42), (b) inverting the MSB (most significant bit) of the SP exponent and using it as the 7 next most significant bits of the EP format, and (c) transferring the MSB of the SP exponent of the MSB of the EP. The operation for converting DP exponents (11 bits) to EP format is analogous. The same exponent conversion techniques are used to reconvert extended format exponents to single and double precision exponents.

Abstract: A carry look-ahead (CLA) adder accommodates a late carry-in from a low-order external 32-bit adder to enable a 96-bit addition to be performed in the same time in which the CLA adder (60) performs a 64-bit addition. Within each adder slice, intermediate group propagate and group generate terms are generated for each bit location in the adder (60), while the adder simultaneously generates an n-bit group propagate and group generate term. The intermediate group propagate and group generate terms are combined with carry-in terms to generate, in parallel, local carry-out terms within each adder slice. The local carry-out terms and intermediate group propagate and group generate terms are used to form a carry chain path which allows the adder to delay the carry-in of an external carry term.

Abstract: A Wallace tree multiplier array (40) performs multiply operations using operands received via a data path (42) having a predetermined height. Rows of carry save adders (CSAs 15'-19") add sets of partial products to generate sets of intermediate summands, which are recursively added to generate a set of final summands. A first group of CSAs form a column which is placed along an axis parallel to the data path (42), and are used to compute a more significant number of bits of each of the summands. The column height of the first group of CSAs is equal to and aligned with the height of the data path (42). A second group of CSAs are placed along an axis perpendicular to the column formed by the first group of CSAs, thereby minimizing the dimension of the multiplier along the data path. The second group of CSAs compute a less significant number of bits of the summands.

Abstract: A recorded iterative multiplier (20) performs an unsigned multiplication operation quickly and with a minimal amount of added circuitry. Multiplier (20) includes a Modified Booth recoder (34) and a plurality of multiplexors (24, 26, 28, 30, and 32) to provide a plurality of partial products. An additional partial product typically generated during a first iteration of the multiplication operation is provided to a multiplexor (44) and a remaining portion of partial products are provided to a summation tree (40) having a symmetrical circuit layout. [Multiplexor (44) stores the additional partial product until summation tree (40) has processed the remaining partial products to provide a first sum.] When summation tree (40) has processed the remaining partial products to provide a first sum, multiplexor (44) provides the additional partial product to a carry save adder (42). The first sum is added to the additional partial product in [a carry-save] adder (42) to provide a first portion of a product.