Abstract: Systems and methods for processing pixels of an image at an imaging hardware device are provided. The method comprises receiving a first pixel. The method further comprises determining a content parameter of the first pixel. The method further comprises, based on the determining, storing the content parameter of the first pixel. The method further comprises initiating a computation of a first output pixel value for the first pixel. The method further comprises receiving a second pixel. The method further comprises determining a content parameter of the second pixel. The method further comprises determining that the second pixel is redundant in response to the content parameter of the second pixel matching the stored content parameter of the first pixel. The method further comprises, in response to the matching, setting a second output pixel value for the second pixel to be equal to the first output pixel value.

Abstract: Various embodiments of methods and systems for data generator driven bus clock voting are disclosed. An exemplary embodiment defines a first timing domain within a system on a chip to comprise a data generating component and a bus that includes a memory management unit. The bus serves to communicatively couple the data generating component to a memory component, such as a DDR. A second timing domain within the system on a chip comprises the memory component. With such a configuration, the embodiment may leverage the clock speed of the data generating component to set a clock speed for components in the first timing domain and, in doing so, the clock speed of the memory management unit is dictated by the first timing domain.

Abstract: Apparatuses and methods to relay a clock signal to clock loads are presented. An apparatus includes a clock spine to conduct a clocking signal. The clock spine includes multiple taps points distributed unevenly on the clock spine. The apparatus further includes multiple clock buffers. Each of the multiple clock buffers is connected to a corresponding one of the multiple tap points. The method includes conducting a clocking signal on a clock spine having multiple taps points. The multiple tap points are distributed unevenly on the clock spine. The method further includes buffering the clocking signal at each of the multiple tap points. Another method includes forming a clock spine to conduct a clocking signal. The clock spine includes multiple taps points. The multiple tap points are distributed unevenly on the clock spine. The method further includes forming multiple clock buffers.

Abstract: Various apparatuses and methods are disclosed for processing texture data compressed with a first compression algorithm and texture data compressed with a second compression algorithm. A processing system may be used to determine whether the compressed texture data is compressed with the first or second compression algorithm, and process the compressed texture data using a decompression algorithm corresponding to the compression algorithm used to compress the texture date.

Abstract: Various apparatuses and methods are disclosed for processing texture data compressed with a first compression algorithm and texture data compressed with a second compression algorithm. A processing system may be used to determine whether the compressed texture data is compressed with the first or second compression algorithm, and process the compressed texture data using a decompression algorithm corresponding to the compression algorithm used to compress the texture date.