Abstract: A fault tolerant control system delivers an embedded functional safety core and a distributed control engine with an onboard communication link in an industrial process control environment. The fault tolerant control system includes a process control workstation connected to a first network and a fault tolerant safety controller connected to a second network, wherein a process controller module, a safety controller module and a field device system integration module are co-located on a power interface board.

Abstract: A fault tolerant control system delivers an embedded functional safety core and a distributed control engine with an onboard communication link in an industrial process control environment. The fault tolerant control system includes a process control workstation connected to a first network and a fault tolerant safety controller connected to a second network, wherein a process controller module, a safety controller module and a field device system integration module are co-located on a power interface board.

Abstract: In a nuclear process control system, a priority logic module (PLM) is provided. The priority logic module comprises a plurality of input ports, each input port associated with one of a plurality of priorities, a plurality of output ports, and a test mode select port associated with a test mode select signal. The test mode select signal selects one of a normal mode or test mode, each mode being associated with matching signals received by the input ports to signals sent by the output ports. The priority logic module further comprises a configurable priority logic circuit, wherein the priority logic circuit maps one of the input ports to one of the output ports.

Abstract: In a nuclear process control system, a priority logic module (PLM) is provided. The priority logic module comprises a plurality of input ports, each input port associated with one of a plurality of priorities, a plurality of output ports, and a test mode select port associated with a test mode select signal. The test mode select signal selects one of a normal mode or test mode, each mode being associated with matching signals received by the input ports to signals sent by the output ports. The priority logic module further comprises a configurable priority logic circuit, wherein the priority logic circuit maps one of the input ports to one of the output ports.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of the time values stored in the memory.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: A measurement system and method for determining a revolution rate of a rotating gear is described. Such a rotating gear can be, for example, a turbine or compressor. The described measurement system and method, for example, can perform highly accurate measurements and can be a fault tolerant system providing high reliability. In one embodiment, an apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: An electric powered vehicle includes a traction motor powered from a source of switched DC power. The motor includes a tachometer for measuring the rotational velocity of the motor and for providing a tachometer signal indicative thereof. A low pass filter low pass filters the tachometer signal and produces a reference tachometer signal. A summing circuit combines the tachometer signal and the reference tachometer signal to produce a deviation signal. The deviation signal is provided to a signal processing circuit which includes a comparator and a reference value generator. The comparator compares the output of the summing circuit to a reference value provided by the reference value generator and produces a binary changing signal as a function of the comparison.