Patents by Inventor Ajay Poonjal Pai

Ajay Poonjal Pai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12113000
    Abstract: A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: October 8, 2024
    Assignee: Infineon Technologies AG
    Inventors: Ajay Poonjal Pai, Tino Karczewski, Adrian Lis
  • Publication number: 20230178460
    Abstract: A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.
    Type: Application
    Filed: December 2, 2021
    Publication date: June 8, 2023
    Inventors: Ajay Poonjal Pai, Tino Karczewski, Adrian Lis
  • Publication number: 20230054812
    Abstract: A power semiconductor module includes: first and second substrates; at least one power semiconductor die arranged between and thermally coupled to a first side of each substrate, and electrically coupled to the first side of the first substrate; at least one rivet having a first end arranged on and electrically coupled to the first side of the first substrate; and an encapsulant encapsulating the at least one power semiconductor die, the at least one rivet and the substrates. At least parts of a second side of the substrates are exposed from the encapsulant. A second end of the at least one rivet is exposed at the encapsulant and configured to accept a press fit pin such that the at least one power semiconductor die can be electrically contacted from the outside.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 23, 2023
    Inventors: Ajay Poonjal Pai, Tao Hong, Adrian Lis, Oliver Markus Kreiter, Matthias Rose