Patents by Inventor Ajay Tomar
Ajay Tomar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9875333Abstract: The present disclosure relates to a system and method for electronic design automation. Embodiments may include receiving, using at least one processor, an electronic design and determining one or more graph based analysis (“GBA”) violating nodes associated with the electronic design. Embodiments may include identifying a non-covered violating node from the GBA violating nodes and determining a worst timing path through the non-covered violating node. Embodiments may further include invoking a path-based analysis (“PBA”) on the worst timing path and determining if the worst timing path satisfies the PBA analysis.Type: GrantFiled: January 19, 2016Date of Patent: January 23, 2018Assignee: Cadence Design Systems, Inc.Inventors: Sourabh Kumar Verma, Naresh Kumar, Ajay Tomar, Rakesh Agarwal, Umesh Gupta, Manish Bansal, Kaustav Guha, Prashant Sethia
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Patent number: 9841802Abstract: Methods, systems, and devices are described for managing wake locks in a wireless communication device. The described methods, systems and devices may enable a wireless communication device to monitor activity of an application for which a wake lock is held. The described approach may manage the wake lock based at least in part on the activity or inactivity of the application. For example, when the application is inactive or has activity below a particular threshold for a certain amount of time, the described approach may determine to release the wake lock.Type: GrantFiled: February 20, 2014Date of Patent: December 12, 2017Assignee: QUALCOMM IncorporatedInventors: Hussein Emami, Mustafa Saglam, Ankur Gupta, Ajay Tomar, Andrew Timothy Hunter, Manish Tripathi, Alejandro Raul Holcman, Daniel Holman Agre
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Publication number: 20150234442Abstract: Methods, systems, and devices are described for managing wake locks in a wireless communication device. The described methods, systems and devices may enable a wireless communication device to monitor activity of an application for which a wake lock is held. The described approach may manage the wake lock based at least in part on the activity or inactivity of the application. For example, when the application is inactive or has activity below a particular threshold for a certain amount of time, the described approach may determine to release the wake lock.Type: ApplicationFiled: February 20, 2014Publication date: August 20, 2015Applicant: QUALCOMM IncorporatedInventors: Hussein Emami, Mustafa Saglam, Ankur Gupta, Ajay Tomar, Andrew Timothy Hunter, Manish Tripathi, Alejandro Raul Holcman, Daniel Holman Agre
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Patent number: 8590815Abstract: Steel rod stock is shaped into a fuel injector tip having a central axis and including a shank extending between a mating end and a nozzle end. An inner surface of the fuel injector tip includes a conical needle valve seat and defines a nozzle chamber and a sac on opposite sides of the needle valve seat. The mating end includes a injector stack surface and an injector body contact surface. After shaping the fuel injector tip, it is a case hardened to a hardness in excess of HRC 55. Next, the nozzle end is shaped, after the case hardening step, to include a plurality of nozzle surfaces that each define one of a plurality of nozzle outlets extending between the sac and the outer surface. The inner surface and the nozzle surfaces are then autofrettaged to induce compressive residual stress at the case hardened needle valve seat, the case hardened sac and at least a portion of the nozzle surfaces closest to the sac.Type: GrantFiled: June 24, 2010Date of Patent: November 26, 2013Assignee: Caterpillar Inc.Inventors: Petr Michlik, Ajay Tomar, Dennis H. Gibson
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Publication number: 20110315793Abstract: Steel rod stock is shaped into a fuel injector tip having a central axis and including a shank extending between a mating end and a nozzle end. An inner surface of the fuel injector tip includes a conical needle valve seat and defines a nozzle chamber and a sac on opposite sides of the needle valve seat. The mating end includes a injector stack surface and an injector body contact surface. After shaping the fuel injector tip, it is a case hardened to a hardness in excess of HRC 55. Next, the nozzle end is shaped, after the case hardening step, to include a plurality of nozzle surfaces that each define one of a plurality of nozzle outlets extending between the sac and the outer surface. The inner surface and the nozzle surfaces are then autofrettaged to induce compressive residual stress at the case hardened needle valve seat, the case hardened sac and at least a portion of the nozzle surfaces closest to the sac.Type: ApplicationFiled: June 24, 2010Publication date: December 29, 2011Applicant: CATERPILLAR INC.Inventors: Petr Michlik, Ajay Tomar, Dennis H. Gibson
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Patent number: 8028262Abstract: Methods and systems improve mapping of LUT based FPGAs. In some embodiments, a topological sort is performed on a network to be mapped, whereby the network is represented as a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of individual nodes using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore improves the number of LUTs and the time consumed in the mapping process.Type: GrantFiled: May 8, 2008Date of Patent: September 27, 2011Assignee: Sicronic Remote KG, LLCInventors: Ajay Tomar, Dhabalendu Samanta
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Publication number: 20080209385Abstract: Methods and systems improve mapping of LUT based FPGAs. In some embodiments, a topological sort is performed on a network to be mapped, whereby the network is represented as a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of individual nodes using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore improves the number of LUTs and the time consumed in the mapping process.Type: ApplicationFiled: May 8, 2008Publication date: August 28, 2008Applicant: Sicronic Remote KGInventors: Ajay Tomar, Dhabalendu Samanta
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Patent number: 7415681Abstract: A method and system for improved optimal mapping of LUT based FPGA's. The invention comprises performing a topological sort on the network to be mapped, whereby the network is represented in form of a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of each node using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore optimizing the number of LUT's and the time consumed in the mapping process.Type: GrantFiled: December 29, 2004Date of Patent: August 19, 2008Assignee: Sicronic Remote KG, LLCInventors: Ajay Tomar, Dhabalendu Samanta
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Patent number: 7191427Abstract: The method for mapping a logic circuit to a plurality of interconnectable, programmable look up tables (LUT) elements includes forming logic element groups including individual logic elements and/or previously formed logic element groups that are capable of being accommodated within the fanin and/or fanout capacity of a target LUT. The method further includes mapping the formed logic element group to the target LUT, and repeating the process for forming logic element groups and mapping to target LUTs for the entire network in a manner such that at each stage only the unmapped logic element/elements and mapped logic element groups of the previous stage are considered for mapping.Type: GrantFiled: April 23, 2004Date of Patent: March 13, 2007Assignee: STMicroelectonics PVT Ltd.Inventors: Sunil Kumar Sharma, Ajay Tomar, Dhabalendu Samanta
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Patent number: 7188328Abstract: A method for finding a maximum volume and minimum cutset in a network of interconnected nodes is provided. The method is applicable to systems that can be reduced to such a network, including telecommunication networks, traffic networks, computer networks, layouts, hydraulic networks, etc. An equivalent network is derived by replacing all nodes other then the source and sink by two interconnected nodes. A conventional method applies an augmenting path algorithm that identifies a cutset. If the feasible cutset is not achieved then a reduced network is constructed by directly connecting the member nodes of identified cutsets to the source node and repeating the above process for the reduced network until a feasible cutset is achieved.Type: GrantFiled: August 27, 2004Date of Patent: March 6, 2007Assignee: STMicroelectronics Pvt Ltd.Inventors: Sunil Kumar Sharma, Ajay Tomar, Dhabalendu Samanta
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Publication number: 20050235236Abstract: A method for finding a maximum volume and minimum cutset in a network of interconnected nodes is provided. The method is applicable to systems that can be reduced to such a network, including telecommunication networks, traffic networks, computer networks, layouts, hydraulic networks, etc. An equivalent network is derived by replacing all nodes other then the source and sink by two interconnected nodes. A conventional method applies an augmenting path algorithm that identifies a cutset. If the feasible cutset is not achieved then a reduced network is constructed by directly connecting the member nodes of identified cutsets to the source node and repeating the above process for the reduced network until a feasible cutset is achieved.Type: ApplicationFiled: August 27, 2004Publication date: October 20, 2005Applicant: STMicroelectronics Pvt. Ltd.Inventors: Sunil Sharma, Ajay Tomar, Dhabalendu Samanta
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Publication number: 20050156626Abstract: A method and system for improved optimal mapping of LUT based FPGA's. The invention comprises performing a topological sort on the network to be mapped, whereby the network is represented in form of a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of each node using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore optimizing the number of LUT's and the time consumed in the mapping process.Type: ApplicationFiled: December 29, 2004Publication date: July 21, 2005Applicant: STMicroelectronics PVT. LTD.Inventors: Ajay Tomar, Dhabalendu Samanta
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Publication number: 20050039157Abstract: The method for mapping a logic circuit to a plurality of interconnectable, programmable look up tables (LUT) elements includes forming logic element groups including individual logic elements and/or previously formed logic element groups that are capable of being accommodated within the fanin and/or fanout capacity of a target LUT. The method further includes mapping the formed logic element group to the target LUT, and repeating the process for forming logic element groups and mapping to target LUTs for the entire network in a manner such that at each stage only the unmapped logic element/elements and mapped logic element groups of the previous stage are considered for mapping.Type: ApplicationFiled: April 23, 2004Publication date: February 17, 2005Applicant: STMicroelectronics Pvt. Ltd.Inventors: Sunil Sharma, Ajay Tomar, Dhabalendu Samanta