Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

Abstract: Examples described herein relate to a first graphics processing unit (GPU) with at least one integrated communications system, wherein the at least one integrated communications system is to apply a reliability protocol to communicate with a second at least one integrated communications system associated with a second GPU to copy data from a first memory region to a second memory region and wherein the first memory region is associated with the first GPU and the second memory region is associated with the second GPU.

Abstract: Systems, apparatuses and methods may provide for technology that detects a runtime call to a communication library, wherein the runtime call identifies a memory buffer, determines that a class of service (CLOS) attribute is associated with the memory buffer, and issues a driver instruction to modify the CLOS attribute in response to the runtime call.

Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

Abstract: Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

Abstract: Systems, apparatuses and methods may provide for technology that detects a runtime call to a communication library, wherein the runtime call identifies a memory buffer, determines that a class of service (CLOS) attribute is associated with the memory buffer, and issues a driver instruction to modify the CLOS attribute in response to the runtime call.

Abstract: An electronic apparatus may be provided that includes a clock device to provide a clock signal, and a clock gate to receive the clock signal, the clock gate to be selectively provided in an enabled state or a disabled state. The electronic apparatus may also include a controller to determine a frequency transition and to control the clock gate to be in the enabled state or the disabled state based on the determined frequency transition.

Abstract: Power conservation for mobile device displays. An embodiment of a method includes generating display images for a display screen of a mobile device, and transitioning the mobile device to a reduced power consumption state. The reduced power consumption state includes reducing one or more illumination factors for the display screen; and reducing one or more animation factors for the display screen.

Abstract: Power conservation for mobile device displays. An embodiment of a method includes generating display images for a display screen of a mobile device, and transitioning the mobile device to a reduced power consumption state. The reduced power consumption state includes reducing one or more illumination factors for the display screen; and reducing one or more animation factors for the display screen.

Abstract: Power conservation for mobile device displays. An embodiment of a method includes generating display images for a display screen of a mobile device, and transitioning the mobile device to a reduced power consumption state. The reduced power consumption state includes reducing one or more illumination factors for the display screen; and reducing one or more animation factors for the display screen.

Abstract: Power conservation for mobile device displays. An embodiment of a method includes generating display images for a display screen of a mobile device, and transitioning the mobile device to a reduced power consumption state. The reduced power consumption state includes reducing one or more illumination factors for the display screen; and reducing one or more animation factors for the display screen.

Abstract: A method for reducing row noise from a complementary metal oxide semiconductor (CMOS) image sensor is disclosed. The method includes determining a set of row sums for a set of pixel rows in the image sensor and a set of corresponding contributing pixel counts. Then, determining a set of row offset corrections. Finally, adjusting the set of pixel rows by the set of row offset corrections.

Abstract: In an embodiment of the invention, a method of downscaling an original image by generating a number of pixels comprising first, second, and third sets. Each pixel comprises a number of components. The method operates by determining all of the components in each pixel of the first set, determining some of the components in each pixel of the second set, and pixels in the third set having no components determined. The scaled image is thus partially determined, with the second and third sets having missing components. The missing components may then be determined by conventional interpolation. Mathematical operators are applied to regions of the image to yield the first, second and third sets of pixels that define the scaled image, without generating an intermediate image in which all three components are determined. The operators may combine interpolation and low pass filtering using a Hamming filter.