Abstract: An ultrafast non-volatile memory cell for wafer-scale integration includes a voltage divider that outputs an output voltage. The voltage divider includes a reference resistive device that is a reference magnetic tunnel junction or another reference resistive component and a switchable magnetic tunnel junction that includes a free magnet and a fixed magnet. The switchable magnetic tunnel junction configured such that the free magnet is light switchable between a high impedance state and a low impedance state upon application of an electric signal and incident light. A transistor switch is configured to activate the voltage divider for memory write and read operations. A light modulator is in electrical communication with the output voltage from the voltage divider. The light modulator is configured to modulate a guided light beam for memory read operations. Arrays of the memory cells are also provided.

Abstract: A sensing circuit for detecting hardware trojans in a target integrated circuit is provided. The sensing circuit includes an array of magnetic tunnel junction circuits where each magnetic tunnel junction circuit including one or more magnetic tunnel junctions. Characteristically, each magnetic tunnel junction circuit configured to provide data for and/or determine a temperature map or a current map of the target integrated circuit.

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract: Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer.

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract: Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer.

Abstract: One illustrative method disclosed herein includes forming a mandrel structure above a semiconductor substrate, performing an oxidation process to oxidize at least a portion of the mandrel structure so as to thereby define oxidized regions on the mandrel structure, removing the oxidized regions to thereby defined a reduced thickness mandrel structure, forming a plurality of fins on the reduced thickness mandrel structure and performing an etching process to selectively remove at least a portion of the reduced thickness mandrel structure so as to thereby expose at least a portion of each of the fins.