Patents by Inventor Ajit Dubhashi

Ajit Dubhashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10205380
    Abstract: In one implementation, a power converter with over-voltage protection includes a power switch coupled to a power supply through a tank circuit, and a control circuit coupled to a gate of the power switch. The control circuit is configured to turn the power switch OFF based on a current from the tank circuit, thereby providing the over-voltage protection to the power converter. In one implementation, the power converter is a class-E power converter. In one implementation, the control circuit is configured to sense the current from the tank circuit based on a voltage drop across a sense resistor coupled to the power switch.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Thomas J. Ribarich, Jorge Cerezo, Ajit Dubhashi
  • Publication number: 20170170718
    Abstract: In one implementation, a power converter with over-voltage protection includes a power switch coupled to a power supply through a tank circuit, and a control circuit coupled to a gate of the power switch. The control circuit is configured to turn the power switch OFF based on a current from the tank circuit, thereby providing the over-voltage protection to the power converter. In one implementation, the power converter is a class-E power converter. In one implementation, the control circuit is configured to sense the current from the tank circuit based on a voltage drop across a sense resistor coupled to the power switch.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 15, 2017
    Inventors: Thomas J. Ribarich, Jorge Cerezo, Ajit Dubhashi
  • Patent number: 9578692
    Abstract: In one implementation, a power converter with over-voltage protection includes a power switch coupled to a power supply through a tank circuit, and a control circuit coupled to a gate of the power switch. The control circuit is configured to turn the power switch OFF based on a current from the tank circuit, thereby providing the over-voltage protection to the power converter. In one implementation, the power converter is a class-E power converter. In one implementation, the control circuit is configured to sense the current from the tank circuit based on a voltage drop across a sense resistor coupled to the power switch.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Thomas J. Ribarich, Jorge Cerezo, Ajit Dubhashi
  • Publication number: 20130277362
    Abstract: In one implementation, a power converter with over-voltage protection includes a power switch coupled to a power supply through a tank circuit, and a control circuit coupled to a gate of the power switch. The control circuit is configured to turn the power switch OFF based on a current from the tank circuit, thereby providing the over-voltage protection to the power converter. In one implementation, the power converter is a class-E power converter. In one implementation, the control circuit is configured to sense the current from the tank circuit based on a voltage drop across a sense resistor coupled to the power switch.
    Type: Application
    Filed: April 11, 2013
    Publication date: October 24, 2013
    Applicant: International Rectifier Corporation
    Inventors: Thomas J. Ribarich, Jorge Cerezo, Ajit Dubhashi
  • Patent number: 7692316
    Abstract: An audio amplifier assembly that includes a semiconductor package having a semiconductor power die tuned for class D amplifier applications and a conductive clip used for low inductance integration into the amplifier circuit.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: April 6, 2010
    Assignee: International Rectifier Corporation
    Inventors: Jianjun Cao, Jorge Cerezo, Ajit Dubhashi, Qun Zhao
  • Patent number: 7250672
    Abstract: A semiconductor package that includes two semiconductor die each disposed on a respective die pad and a large tracking distance interposed between at least two leads of the package for better creepage characteristics.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: July 31, 2007
    Assignee: International Rectifier Corporation
    Inventors: Mark Pavier, Ajit Dubhashi, Jorge Cerezo, Leigh Cormie, Vijay Bolloju
  • Patent number: 7236340
    Abstract: A switch in an inductive circuit is prevented from avalanche operation when the switch is turned off. By preventing avalanche, the associated EMI is reduced or eliminated. Switch avalanche can be prevented using an active component, such as a transistor, or a passive component, such as a resistor, coupled to the switch gate to control current in the switch gate. By controlling current in the switch gate during turn-off, avalanche operation can be prevented without a significant increase in turn-off energy.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: June 26, 2007
    Assignee: International Rectifier Corporation
    Inventors: Shahin Maloyan, Ajit Dubhashi
  • Patent number: 7227198
    Abstract: A semiconductor package that includes two power semiconductor dies, such as power MOSFET dies, including vertical conduction MOSFETs, arranged in a half-bridge configuration is disclosed. The package may be mounted on a split conductive pad including two isolated die pads, each die pad being electrically connected to the second power electrode of the die that is on it. The split pad may include several conductive leads, including at least one output lead electrically connected to a first electrode of the first semiconductor die on the same side of the die as the control electrode and to the second electrode of the second die located on the opposite side of the second die from the control electrode.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: June 5, 2007
    Assignee: International Rectifier Corporation
    Inventors: Mark Pavier, Ajit Dubhashi, Norman G. Connah, Jorge Cerezo
  • Patent number: 7095099
    Abstract: A low profile semiconductor device package includes a lead frame with terminal leads and two die pads for receiving at least two semiconductor die that are interconnected to form a circuit. A further low profile semiconductor device package includes a lead frame with two die pads for receiving at least two semiconductor die that are interconnected to form a circuit and also has a reduced height through removal of a mounting tab. An example of such device packages is a package that includes first and second MOSFET die, each connected to a respective die pad. The source of one MOSFET is connected to the drain of the other MOSFET, thereby forming a low profile device package that provides a half-bridge circuit. Other example device packages include different arrangements of two interconnected MOSFET die, two interconnected IGBTs, or a combination of a MOSFET die and a diode.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: August 22, 2006
    Assignee: International Rectifier Corporation
    Inventors: Stephen Oliver, Marco Soldano, Mark Pavier, Glyn Connah, Ajit Dubhashi
  • Patent number: 7042730
    Abstract: A power module including a power circuit having heat generating power devices including one or more heatsinks not isolated from the power devices by an insulating body.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: May 9, 2006
    Assignee: International Rectifier Corporation
    Inventors: Bertrand Vaysse, Heny Lin, Thanh Van Tran, Ajit Dubhashi
  • Publication number: 20060087026
    Abstract: An audio amplifier assembly that includes a semiconductor package having a semiconductor power die tuned for class D amplifier applications and a conductive clip used for low inductance integration into the amplifier circuit.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 27, 2006
    Inventors: Jianjun Cao, Jorge Cerezo, Ajit Dubhashi, Qun Zhao
  • Publication number: 20060033122
    Abstract: A semiconductor package which includes two power semiconductor die arranged in a half-bridge configuration.
    Type: Application
    Filed: August 11, 2005
    Publication date: February 16, 2006
    Inventors: Mark Pavier, Ajit Dubhashi, Norman Connah, Jorge Cerezo
  • Patent number: 6969971
    Abstract: A reverse battery protection circuit comprising a first controlled semiconductor switch for providing current to a load and coupled in series with load terminals across which load terminals the load is adapted to be connected and a second controlled semiconductor switch disposed in a series circuit with a free wheeling diode, the series circuit being coupled across the load terminals.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: November 29, 2005
    Assignee: International Rectifier Corporation
    Inventor: Ajit Dubhashi
  • Patent number: 6956359
    Abstract: An inductive load driven by power MOSFETs, such as in a low voltage motor drive, using synchronous rectification to reduce the voltage drop across a body diode of a power MOSFET. A comparative feed back circuit measures voltage across the power MOSFET to determine when the body diode is conducting, and turns the MOSFET ON during conductive cycles, and OFF to block reverse current. The obtained synchronous rectification function is highly sensitive to current flow, while using a very small number of parts in a configuration that has less complexity.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: October 18, 2005
    Assignee: International Rectifier Corporation
    Inventor: Ajit Dubhashi
  • Publication number: 20050151236
    Abstract: A low profile semiconductor device package includes a lead frame with terminal leads and two die pads for receiving at least two semiconductor die that are interconnected to form a circuit. A further low profile semiconductor device package includes a lead frame with two die pads for receiving at least two semiconductor die that are interconnected to form a circuit and also has a reduced height through removal of a mounting tab. An example of such device packages is a package that includes first and second MOSFET die, each connected to a respective die pad. The source of one MOSFET is connected to the drain of the other MOSFET, thereby forming a low profile device package that provides a half-bridge circuit. Other example device packages include different arrangements of two interconnected MOSFET die, two interconnected IGBTs, or a combination of a MOSFET die and a diode.
    Type: Application
    Filed: November 12, 2004
    Publication date: July 14, 2005
    Inventors: Stephen Oliver, Marco Soldano, Mark Pavier, Glyn Connah, Ajit Dubhashi
  • Publication number: 20050133902
    Abstract: A semiconductor package that includes two semiconductor die each disposed on a respective die pad and a large tracking distance interposed between at least two leads of the package for better creepage characteristics.
    Type: Application
    Filed: November 12, 2004
    Publication date: June 23, 2005
    Inventors: Mark Pavier, Ajit Dubhashi, Jorge Cerezo, Leigh Cormie, Vijay Bolloju
  • Patent number: 6867576
    Abstract: A small capacity FET is coupled to a power MOSFET to sense voltage across the power MOSFET for determining current carried through the power MOSFET. The FET is turned on when the power MOSFET is turned on to obtain a sense voltage that is fed to a comparator to determine if the voltage across the power MOSFET exceeds a threshold voltage. The output of the comparator is used to shut off the drive for the power MOSFET if the threshold is exceeded. The voltage across the FET can be used with a temperature sense and knowledge of the FET RDSON to obtain a sense feedback of current through the power MOSFET. The FET is controlled with a delay to turn on after the power MOSFET is turned on, and turns off before the power MOSFET turns off.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: March 15, 2005
    Assignee: International Rectifier Corporation
    Inventor: Ajit Dubhashi
  • Patent number: 6819095
    Abstract: A semiconductor module has a conductive heat sink base which receives a power semiconductor and a printed circuit board mounted above the heat sink and carrying control circuits for the power semiconductor. A rigid L-shaped terminal connected to one electrode of the power semiconductor is mounted on the base and extends upward and adjacent an edge of the printed circuit board. A Hall sensor is mounted on the printed circuit board and is disposed in and intercepts the magnetic field produced by current in the terminal. Magnetic bodies are mounted on opposite sides of the Hall element to concentrate the magnetic field through the Hall sensor.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: November 16, 2004
    Assignee: International Rectifier Corporation
    Inventors: Ajit Dubhashi, Shahin Maloyan, Joshua Polack
  • Publication number: 20040145353
    Abstract: A reverse battery protection circuit comprising a first controlled semiconductor switch for providing current to a load and coupled in series with load terminals across which load terminals the load is adapted to be connected and a second controlled semiconductor switch disposed in a series circuit with a free wheeling diode, the series circuit being coupled across the load terminals.
    Type: Application
    Filed: December 2, 2003
    Publication date: July 29, 2004
    Applicant: International Rectifier Corporation
    Inventor: Ajit Dubhashi
  • Patent number: 6744136
    Abstract: A liquid cooled electronic device and a method for sealing a liquid cooled electronic device are disclosed. The liquid cooled electronic device has at least one heat generating electronic device suspended in an electrically insulative heat transfer fluid. The heat generating device or devices are electrically connected to at least two electrodes, which pass through and are sealed in electrically insulating portion of a sealed housing that encloses the electrically insulative heat transfer fluid. At least one thermally conductive surface is in direct contact with the electrically insulative heat transfer fluid, and at least one thermally conductive surface is sealed to the remainder of the housing, for example.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: June 1, 2004
    Assignee: International Rectifier Corporation
    Inventor: Ajit Dubhashi