Abstract: Methods of encoding a video stream in a video encoder and decoding an encoded video stream in a video decoder using a low complexity large transform are provided. An encoding method includes receiving an n×n residual block in a transform component of the video encoder, and transforming the n×n residual block using an n×n transform to generate an n×n transform coefficient block, wherein the n×n transform is based on (n/m*n/m) m×m Hadamard transforms and (m*m) (n/m)×(n/m) discrete cosign transforms, wherein m<n. A decoding method includes receiving an n×n transform coefficient block in an inverse transform component of the video decoder, and applying an n×n inverse transform to the n×n transform coefficient block to reconstruct an n×n residual block, wherein the n×n inverse transform is based on (n/m*n/m) m×m Hadamard transforms and (m*m) (n/m)×(n/m) inverse discrete cosign transforms, wherein m<n.

Abstract: Methods of encoding a video stream in a video encoder and decoding an encoded video stream in a video decoder using a low complexity large transform are provided. An encoding method includes receiving an n×n residual block in a transform component of the video encoder, and transforming the n×n residual block using an n×n transform to generate an n×n transform coefficient block, wherein the n×n transform is based on (n/m*n/m) m×m Hadamard transforms and (m*m) (n/m)×(n/m) discrete cosign transforms, wherein m<n. A decoding method includes receiving an n×n transform coefficient block in an inverse transform component of the video decoder, and applying an n×n inverse transform to the n×n transform coefficient block to reconstruct an n×n residual block, wherein the n×n inverse transform is based on (n/m*n/m) m×m Hadamard transforms and (m*m) (n/m)×(n/m) inverse discrete cosign transforms, wherein m<n.

Abstract: In one example, a device for retrieving video data includes a display interface coupled to a display, a memory configured to store video data, and one or more processors configured to determine a plurality of regions of video data to be displayed via the display, retrieve video data having a first quality for a first subset of the plurality of regions at which a visual focus of a user is directed, retrieve video data having a second quality for a second subset of the plurality of regions that neighbor the first subset of the plurality of regions, wherein the second quality is lower than the first quality, and retrieve video data having a third quality for a third subset of the plurality of regions that is outside the first subset and the second subset, wherein the third quality is lower than the second quality.

Abstract: In one example, a device for retrieving video data includes a display interface coupled to a display, a memory configured to store video data, and one or more processors configured to determine a plurality of regions of video data to be displayed via the display, retrieve video data having a first quality for a first subset of the plurality of regions at which a visual focus of a user is directed, retrieve video data having a second quality for a second subset of the plurality of regions that neighbor the first subset of the plurality of regions, wherein the second quality is lower than the first quality, and retrieve video data having a third quality for a third subset of the plurality of regions that is outside the first subset and the second subset, wherein the third quality is lower than the second quality.

Abstract: A method includes receiving, at a device, a plurality of image frames corresponding to a video stream. The plurality of image frames include a first image frame having a first resolution and a second image frame having a second resolution that is lower than the first resolution. The method also includes detecting, at the device, a trigger by analyzing the second image frame. The method further includes designating, at the device, the first image frame as an action frame based on the trigger.

Abstract: A method includes receiving, at a device, a plurality of image frames corresponding to a video stream. The plurality of image frames include a first image frame having a first resolution and a second image frame having a second resolution that is lower than the first resolution. The method also includes detecting, at the device, a trigger by analyzing the second image frame. The method further includes designating, at the device, the first image frame as an action frame based on the trigger.

Abstract: Methods of encoding a video stream in a video encoder and decoding an encoded video stream in a video decoder using a low complexity large transform are provided. An encoding method includes receiving an n×n residual block in a transform component of the video encoder, and transforming the n×n residual block using an n×n transform to generate an n×n transform coefficient block, wherein the n×n transform is based on (n/m*n/m) m×m Hadamard transforms and (m*m) (n/m)×(n/m) discrete cosign transforms, wherein m<n. A decoding method includes receiving an n×n transform coefficient block in an inverse transform component of the video decoder, and applying an n×n inverse transform to the n×n transform coefficient block to reconstruct an n×n residual block, wherein the n×n inverse transform is based on (n/m*n/m) m×m Hadamard transforms and (m*m) (n/m)×(n/m) inverse discrete cosign transforms, wherein m<n.

Abstract: Methods of encoding a video stream in a video encoder and decoding an encoded video stream in a video decoder using a low complexity large transform are provided. An encoding method includes receiving an n×n residual block in a transform component of the video encoder, and transforming the n×n residual block using an n×n transform to generate an n×n transform coefficient block, wherein the n×n transform is based on (n/m*n/m) m×m Hadamard transforms and (m*m) (n/m)×(n/m) discrete cosign transforms, wherein m<n. A decoding method includes receiving an n×n transform coefficient block in an inverse transform component of the video decoder, and applying an n×n inverse transform to the n×n transform coefficient block to reconstruct an n×n residual block, wherein the n×n inverse transform is based on (n/m*n/m) m×m Hadamard transforms and (m*m) (n/m)×(n/m) inverse discrete cosign transforms, wherein m<n.

Abstract: Methods of encoding a video stream in a video encoder and decoding an encoded video stream in a video decoder using a low complexity large transform are provided. An encoding method includes receiving an n×n residual block in a transform component of the video encoder, and transforming the n×n residual block using an n×n transform to generate an n×n transform coefficient block, wherein the n×n transform is based on (n/m*n/m) m×m Hadamard transforms and (m*m) (n/m)×(n/m) discrete cosign transforms, wherein m<n. A decoding method includes receiving an n×n transform coefficient block in an inverse transform component of the video decoder, and applying an n×n inverse transform to the n×n transform coefficient block to reconstruct an n×n residual block, wherein the n×n inverse transform is based on (n/m*n/m) m×m Hadamard transforms and (m*m) (n/m)×(n/m) inverse discrete cosign transforms, wherein m<n.

Abstract: A circuit which first shifts both a dividend and a divisor by an extra bit such that a 1-bit shift can be avoided after subtraction of the shifted values of dividend and the divisor, while performing a conditional subtraction instruction. The shifted divisor can conveniently replace the dividend as required for the instruction. The approach can be used to implement, among others, 2N-bit/N-bit (denoted 2N/N) division using an N-bit ALU, N/N division using N-bit ALU. The division can be implemented for all possible values of N without requiring substantially more complexity in the implementation.

Abstract: A log shifter shifting an operand left or right while minimizing the number of multiplexor stages. The log shifter may contain a set of multiplexor stages, with at least one multiplexor stage shifting a data value to the right and at least one other multiplexor stage shifting to the right. Left and right shifts may thus be obtained by using a single set of multiplexor stages. As a result, time delays and area consumed may be reduced when the upper/lower end of a desired shift value range does not equal 2Q?1, wherein Q equals an integer.

Abstract: A circuit which first shifts both a dividend and a divisor by an extra bit such that a 1-bit shift can be avoided after subtraction of the shifted values of dividend and the divisor, while performing a conditional subtraction instruction. The shifted divisor can conveniently replace the dividend as required for the instruction. The approach can be used to implement, among others, 2N-bit/N-bit (denoted 2N/N) division using an N-bit ALU, N/N division using N-bit ALU. The division can be implemented for all possible values of N without requiring substantially more complexity in the implementation.

Abstract: A log shifter shifting an operand left or right while minimizing the number of multiplexor stages. The log shifter may contain a set of multiplexor stages, with at least one multiplexor stage shifting a data value to the right and at least one other multiplexor stage shifting to the right. Left and right shifts may thus be obtained by using a single set of multiplexor stages. As a result, time delays and area consumed may be reduced when the upper/lower end of a desired shift value range does not equal 2Q−1, wherein Q equals an integer.