Abstract: Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewing after chip placement.

Abstract: Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewing after chip placement.

Abstract: A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium.

Abstract: A device and process for applying mixtures of adhesive formulations combined with solder flux such that flip chips may be rapidly encapsulated with such combinations without interfering with subsequent wafer processing steps are provided. Also provided is a wafer stencil designed in such a manner that the saw kerf lines separating individual chip dies are protected from coming into contact with the formulation. Extrusion screening using such wafer stencil is also provided.

Abstract: A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium.

Abstract: A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium.

Abstract: A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium.

Abstract: A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium.

Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.

Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.

Abstract: Plated thru holes in a printed circuit card or board are filled with solder to provide as void free as possible solder fill. According to one method, an adhesive film is provided on the bottom side of a circuit card or board containing plated thru holes. A plurality of solder balls are then provided within at least one thru hole of the card or board. The total volume of the solder balls is greater than the volume of the plated thru hole. The solder balls are reflowed to thereby fill the plated thru hole with solder and provide solder on top of the thru hole.According to another method, a solder ball is provided above and in contact with a plated thru hole. The volume of the solder ball is greater than the volume of the plated thru hole. The solder ball is reflowed to thereby fill the plated thru hole with solder, and to provide solder both above and below the plated thru hole.

Abstract: A printed circuit board or card for direct chip attachment that includes at least one power core, at least one signal plane that is adjacent to the power core, and plated through holes for electrical connection is provided. In addition, a layer of dielectric material is adjacent the power core and a circuitized conductive layer is adjacent the dielectric material, followed by a layer of photosensitive dielectric material adjacent the conductive layer. Photodeveloped blind vias for subsequent connection to the power core and drilled blind vias for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.

Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.