Patents by Inventor Ajit M. Dubey

Ajit M. Dubey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11557420
    Abstract: Methods of coupling inductors in an IC device using interconnecting elements with solder caps and the resulting device are disclosed. Embodiments include forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: January 17, 2023
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tak Ming Mak, Ajit M. Dubey
  • Publication number: 20170154722
    Abstract: Methods of coupling inductors in an IC device using interconnecting elements with solder caps and the resulting device are disclosed. Embodiments include forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Inventors: Tak Ming MAK, Ajit M. DUBEY
  • Patent number: 9646758
    Abstract: Methods of coupling inductors in an IC device using interconnecting elements with solder caps and the resulting device are disclosed. Embodiments include forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: May 9, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tak Ming Mak, Ajit M. Dubey
  • Publication number: 20170018348
    Abstract: Methods of coupling inductors in an IC device using interconnecting elements with solder caps and the resulting device are disclosed. Embodiments include forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other.
    Type: Application
    Filed: July 14, 2015
    Publication date: January 19, 2017
    Inventors: Tak Ming MAK, Ajit M. DUBEY
  • Patent number: 6621043
    Abstract: A method of calibrating a laser utilized in a laser element cutting system utilizing a mechanical gauge having pairs of metal pads formed in rows and columns on a substrate material. The height of the metal pads varies in each row with each column having the same height. The depth of the substrate material under the metal pads varies. The mechanical gauge is subjected to a laser cut process and the mechanical gauge is illuminated by a light source. The light shining through positions of metal pads indicates that the metal pad and the underlying substrate material have been cut. The depth of cut is determined from the thickness of the metal layer and the thickness of the substrate material that have been cut.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: September 16, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Don Lambert, Valerie Vivares, Ajit M. Dubey
  • Patent number: 6591992
    Abstract: A boat for cleaning semiconductor packages, including cleaning ball grid array packages in centrifugal cleaners. The boat includes a bottom plate with receptacles for receiving semiconductor packages and a top plate having through holes, where each through hole is smaller than the receptacle with which it corresponds in the bottom plate. An alignment mechanism ensures that the top plate is aligned with the bottom plate in a manner that results in each through hole being positioned directly over a respective one of the receptacles. An attachment mechanism releasably attaches the top plate to the bottom plate in a co-planar relationship that results in the presence of a vertical space between the two plates.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: July 15, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ajit M. Dubey, Raj N. Master, Ong Ot, Chan Cs
  • Patent number: 6446818
    Abstract: A boat for cleaning semiconductor packages, including cleaning ball grid array packages in centrifugal cleaners. The boat includes a bottom plate with receptacles for receiving semiconductor packages and a top plate having through holes, where each through hole is smaller than the receptacle with which it corresponds in the bottom plate. An alignment mechanism ensures that the top plate is aligned with the bottom plate in a manner that results in each through hole being positioned directly over a respective one of the receptacles. An attachment mechanism releasably attaches the top plate to the bottom plate in a co-planar relationship that results in the presence of a vertical space between the two plates.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: September 10, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ajit M. Dubey, Raj N. Master, Ot Ong, C S Chan
  • Patent number: 6333210
    Abstract: A method of maintaining z-height of an integrated circuit component, such as a multi-chip module, a chip or a die, and of visualizing alignment of an integrated circuit package during positioning of an integrated circuit component, is disclosed. The method maintains the z-height of an integrated circuit component during a solder reflow step by applying high-melting solder balls to interconnect pads on the package substrate surface. Such high-melting solder balls, for instance 90 Pb/10 Sn, do not collapse at temperatures sufficient to accomplish reflowing. The high-melting solder balls also make convenient visualization marks for alignment of the package substrate on an integrated circuit component placement tool, such as a die placement tool. A package substrate bearing high-melting solder balls in a pre-determined pattern is easily aligned by an integrated circuit placement tool using machine vision.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: December 25, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ajit M. Dubey, Raj N. Master