Abstract: A design for test focused tester has a single printed circuit board tester architecture. By focusing on design for test testing and eliminating functional testing, the design for test focused tester reduces or eliminates requirements for high speed, precision signal formatting and timing circuitry that require a multiple board architecture interconnected via a high speed backplane. The single board architecture places a vector sequencer and vector memory close to the device under test, which provides short, consistent signal paths to the device and eliminates the need for dead cycles and synchronization between tester boards.

Abstract: A modular tester architecture allows end-users to mix-and-match scan chain modules and clock driver modules. Modules are interconnected via a synchronization bus allowing the test modules to synchronize with each other so that each can perform its portion of the overall test at the proper time in relation to the testing performed by other modules. The modules can include a BIST driver module, a data acquisition module, networking interface modules, a controller module, a current measurement module, and a DC parametrics module, among others.

Abstract: A modular tester architecture allows end-users to mix-and-match scan chain modules and clock driver modules. Modules are interconnected via a synchronization bus allowing the test modules to synchronize with each other so that each can perform its portion of the overall test at the proper time in relation to the testing performed by other modules. The modules can include a BIST driver module, a data acquisition module, networking interface modules, a controller module, a current measurement module, and a DC parametrics module, among others.

Abstract: An audio/video processing engine that is programmable for processing digital video and digital audio simultaneously, either in parallel or concurrently, has an audio/video I/O processor that communicates with a single programmable hardware processor having reconfigurable logic blocks. The single programmable hardware processor communicates with both a general purpose processor and an optional digital signal processor for adjunct processing. The general purpose processor has a flash memory for initializing the programmable elements of the audio/video processing engine and has data links for remote accessing for programming, control and monitoring. The flash memory is accessible by the single programmable hardware processor, and may be reloaded remotely via the general purpose processor.

Abstract: A DFT-focused tester has a single printed circuit board tester architecture. By focusing on DFT testing and eliminating functional testing, the DFT-focused tester reduces or eliminates requirements for high speed, precision signal formatting and timing circuitry that require a multiple board architecture interconnected via a high speed backplane. The single board architecture places a vector sequencer and vector memory close to the device under test, which provides short, consistent signal paths to the device and eliminates the need for dead cycles and synchronization between tester boards.

Abstract: A data file containing metadata and/or control data is synchronized with associated audio/video data by subliminally embedding a key in a frame of the audio/video. The key indicates the location of the data file and a time after the embedded frame in which the data file is to be activated to be in synchronism with the audio/video. The data file is accessed via an alternate channel and held in a buffer until the time indicated by the key. The metadata from the data file is played out for display in synchronism with the associated audio/video data, and instructions contained in the control data are executed in synchronism with the associated audio/video data.

Abstract: An audio/video processing engine uses a single programmable hardware processor having reconfigurable logic blocks, such as a RAM-based field programmable gate array, to process in real time both digital video and digital audio received from respective video and audio I/O processors and also to output the processed digital video and digital audio through the video and audio I/O processors. The single programmable hardware processor communicates with an optional digital signal processor and a general purpose processor having a flash memory for adjunct processing. The general purpose processor is remotely accessible for programming, control and monitoring functions, and the flash memory provides boot up for the general process processor as well as information for memory associated with the programmable hardware processor and for the digital signal processor. The flash memory also is accessible by the programmable hardware processor.