Abstract: Contamination of LPCVDBP TEOS films is reduced by preventing volatile compounds, resulting from reactions of the residue in the outlet of the furnace from reaching the deposition portion of the furnace where they would otherwise react with the deposition gases to produce chemically generated particles which contaminate the dielectric film.

Abstract: An integrated circuit and method of fabrication are disclosed. The invention provides an etch-stop layer between a plug formed in a via and an overlying runner. The etch stop layer serves a variety of functions, including protecting the plug during the etching process which defines the runner.

Abstract: A process for the formation of material layers such as amorphous silicon is disclosed. When a precursor gas such as silane is utilized to form amorphous silicon, silicon crystals are often formed on top of the amorphous silicon layer. The crystals are created by the presence of low pressure silane in the reactor at the end of the deposition cycle. Formation of crystals is inhibited by lowering the temperature before silane flow is terminated.

Abstract: A method of forming silicon dioxide layers by bias ECR is described. The layers are formed by reacting oxygen with TEOS or TMCTS. High-quality, void-free layerc can be formed over conductor patterns having high-aspect-ratio intermetallic spacings.

Abstract: When forming a metallization layer in integrated-circuit semiconductor device fabrication, metal such as tungsten, for example, adheres poorly to dielectrics such as, e.g., silicon oxide, and tends to flake off from wafer areas not covered by a glue layer- such areas typically including the backside and the edge of the wafer, and clip marks on the face of the wafer. The invention prevents flaking by processing including: forming an adhesive or glue layer on the dielectric, forming a metal layer, forming a protective layer on metal on the glue layer, and etching to remove metal not covered by the protective layer.

Abstract: A planar surface is produced in integrated circuit processing by patterning a bilevel structure of a conductor and a sacrificial layer followed by directional deposition of a dielectric and lift off of the sacrificial layer. An additional dielectric layer may now be deposited if desired.

Abstract: Disclosed is an integrated circuit manufacturing technique that relies on the use of polysilicon fillets for overcoming the well known adverse effects of steep sidewalls produced by anisotropic etching processes and undercuts produced by anisotropic etching of multilayers.

Abstract: The specification describes a process for treating patterned VLSI lithographic masks to retain their shape during processing of VLSI wafers. The process avoids the common postbake treatment which tends to cause sagging of the sidewalls of the mask. Retention of vertical sidewalls on the mask edges has been found important for producing vertical sidewalls in layers that are being anisotropically etched.

Abstract: The manufacture of VLSI devices is facilitated by a method for chlorine reactive sputter etching of silicon materials in a plasma reactor that has been passivated by a previous etching operation involving a fluorine-containing gas. The passivated reactor is reactivated for chlorine reactive sputter etching by the generation of a boron trichloride plasma in the reactor. In the preferred embodiment, a mixture of boron trichloride and chlorine is used to initiate the etching of the silicon material before pure chlorine is used to complete the etch. The invention permits silicon materials to be etched in a reactor in which chlorine and fluorine-containing gases are used sequentially.