Patents by Inventor Ajit Trivedi

Ajit Trivedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Placement of sacrificial solder balls underneath the PBGA substrate
    Patent number: 7227268
    Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: June 5, 2007
    Assignee: International Business Machines Corporation
    Inventors: Chi Shih Chang, William T. Chen, Ajit Trivedi
  • Placement of sacrificial solder balls underneath the PBGA substrate
    Publication number: 20050063165
    Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.
    Type: Application
    Filed: October 29, 2004
    Publication date: March 24, 2005
    Inventors: Chi Chang, William Chen, Ajit Trivedi
  • Placement of sacrificial solder balls underneath the PBGA substrate
    Patent number: 6829149
    Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: December 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Chi Shih Chang, William T. Chen, Ajit Trivedi
  • Proper choice of the encapsulant volumetric CTE for different PGBA substrates
    Patent number: 6353182
    Abstract: The present invention describes a method and apparatus for packaging a flip chip by matching the z-direction CTE of the IC solder joint with the z-direction CTE of the encapsulant. Consideration of the z-direction CTE's is important when determining the volumetric CTE of the encapsulant. This invention first requires a determination of the z-direction CTE of the IC solder joint and a determination of the z-direction CTE of the encapsulant. The invention next matches the z-direction CTE of the IC solder joint to the z-direction CTE of the encapsulant. The matching of the two z-direction CTE's reduces the z-direction tensile or compression stresses on the IC solder joint and the encapsulant.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: March 5, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chi Shih Chang, William T. Chen, Ajit Trivedi
  • Relocating the neutral plane in a PBGA substrate to eliminate chip crack and interfacial delamination
    Patent number: 6255599
    Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: July 3, 2001
    Assignee: IBM
    Inventors: Chi Shih Chang, William T. Chen, Ajit Trivedi
  • Construction of PBGA substrate for flip chip packing
    Patent number: 5959348
    Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: September 28, 1999
    Assignees: International Business Machines Corporation, Sematech, Inc.
    Inventors: Chi Shih Chang, William T. Chen, Ajit Trivedi