Abstract: An integrated circuit package comprising a substrate, and a chip die mounted on the substrate. The substrate includes electrically conductive traces, a set of primary interconnects arranged to couple to output pads of the chip die, and a set of secondary interconnects for coupling the package to external circuitry. A first subset of the primary interconnects are electrically coupled to the secondary interconnects and a second subset of the primary interconnects are thermally coupled using thermal vias to the opposite surface of the substrate. The output pads associated with the first subset of the primary interconnects therefore function as electrically interconnecting pads whereas the output pads associated with the second subset of the primary interconnects function as non-electrically interconnecting thermal-dissipation pads.