Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

Abstract: A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A snapback leg in curves capable of being produced in accordance with one or more aspects of the present invention is removed, and a trigger voltage at which the device turns on is thereby reduced so as to be less than a second voltage corresponding to a second breakdown region.

Abstract: A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A snapback leg in curves capable of being produced in accordance with one or more aspects of the present invention is removed, and a trigger voltage at which the device turns on is thereby reduced so as to be less than a second voltage corresponding to a second breakdown region.

Abstract: The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10) comprising at least one input element (20) is protected by a protective circuit (40). The protective circuit (40) is operable to protect the integrated circuit (10) from damage due to electrostatic discharge and may be coupled to the input element (20). The protective circuit (40) comprises a lateral NPN transistor (T1) coupled to the input element (20) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (20). The protective circuit (40) also may comprise a lateral PNP transistor (T2) coupled to the input element (20) and to the lateral NPN transistor (T1). The lateral PNP transistor (T2) is operable to aid in raising a potential of the base of the lateral NPN transistor (T1).

Abstract: An operational lifetime, and also performance characteristics, can be accurately predicted for an experimental transistor design (10) and a specified set of fabrication process conditions (117), without actually fabricating and testing a physical transistor made according to the particular design data and process conditions. With respect to the prediction of an operational lifetime, the operational lifetime can be expressed as a function of the size of a gate overlap (12) of the transistor, and this relationship is valid throughout a selected semiconductor technology for which the transistor is designed. The size of the gate overlap is determined by selecting a combinations of values for two process conditions.

Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

Abstract: An ESD protection circuit (100) and method is described herein. A lateral npn transistor (104) is connected between an I/O pad (110) and ground (GND). A substrate biasing circuit (150) increases the voltage across a substrate resistance (114) during an ESD event by conducting current through the substrate. This, in turn, triggers the lateral npn (104) which clamps to voltage at the pad (110) and dissipated the ESD current. The lateral npn (104) is the primary protection device for dissipating ESD current.

Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.

Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.

Abstract: A protection device for trench isolated technologies. The protection device includes a lateral SCR (100) that incorporates a triggering MOS transistor (120) with a first gate electrode (116) connected to the cathode (112) of the SCR (100). The anode (110) of the lateral SCR (100) is separated from the nearest source/drain region (122) of the triggering MOS transistor (120) by a second gate electrode (132) rather than by trench isolation. By using the second gate electrode (132) for isolation instead of trench isolation, the surface conduction of the lateral SCR (100) in unimpeded.

Abstract: An ESD protection circuit for dual 3V/5V supply devices. ESD protection circuit 10 comprises a switching element 12 connected between a bond pad 14 and primary protection device 16. Primary protection device 16 comprises MOS circuitry designed for 3V operation that suffers from oxide reliability problems when 5V signals are applied directly. Switching element 12 separates the primary protection device 16 from 5V signals which may appear at bond pad 14.

Abstract: A method for achieving improving ESD protection in integrated circuits. Capacitance associated with a power supply plays an important role in ESD protection and increasing Vcc.sub.-- c capacitance by integrating distributed capacitors as junction capacitors, or MOS capacitors along Vcc and grounded n+ diffusion parallel runs improves protection against ESD and EOS. Additionally, at least a pair of antiparallel diodes interposed between the periphery voltage source and internal core circuitry voltage provides an added noise margin.

Abstract: One embodiment of the instant invention is a charge-induced damage protection device (100 or 500) for protecting a semiconductor device (200) which is formed on a common substrate with the protection device, the protection device comprising: a region in the substrate; and wherein the region is accessible to electromagnetic energy during processing in which charges may collect on conductive material such that the protective device turns on at a lower voltage due to introduction of the electromagnetic energy to the region so as to protect the semiconductor device from the charge-induced damage. Preferably, the protection device is selected from the group consisting of: a diode, a thyristor, a bidirectional thyristor, a bipolar transistor, and a polymer that becomes more conductive upon being illuminated by electromagnetic energy.

Abstract: An ESD protected semiconductor circuit and the ESD protection circuit. The protected circuit includes a terminal, a semiconductor device coupled to the terminal and an ESD protection circuit. The ESD protection circuit includes a substrate of a first conductivity type and has a surface. A first well of conductivity type opposite to the first conductivity type is disposed within the substrate and extends to the surface. A second well of the first conductivity type is disposed within the first well and is spaced from the substrate and extending to the surface. A third region of the opposite conductivity type is disposed within the second well and is spaced from the first well and extending to the surface. At least one of the substrate or the third region is coupled to the terminal.

Abstract: Bias circuits which define control terminal voltages in a cascoded nMOS ESD protection circuit, such that the circuit is in high impedance state (OFF) during normal operation, and low impedance (ON) during an ESD event. G1 and G2 are the driver circuits which define V3 and V4 during an ESD event at the pad. During normal operation, V3 and/or V4 are high and no current flows between the pad and V.sub.SS. During an ESD event, V3 and V4 are high and both devices conduct MOS current as the lateral NPNs turn on. Diode D1 conducts current to charge C.sub.c, the chip capacitance, raising V.sub.DD, enabling G1 and G2 to turn on and raise V3 and V4 to levels greater than the nMOS threshold voltage.

Abstract: A protection device comprising a gate-coupled silicon-controlled rectifier (SCR) (100), SCR (100) comprises an anode (105) formed in n-well (104) and connected to a pad (128) and a cathode (111) connected to ground. A gate-coupled NMOS transistor (120) has a gate (116) connected through a resistive element (118) to ground. A n+ region (112) forms both the cathode (111) and a source of the NMOS transistor (120). N-well (104) forms the drain. Stress voltage is coupled from pad (128) to gate electrode (116) causing NMOS transistor (120) to conduct. This, in turn, triggers SCR (100) which dissipates the stress current at the pad (128). The coupled voltage at gate electrode (116) dissipates within a designed time constant through resistive element (118).

Abstract: The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically <0.5 pF) and series resistance (typically <0.5 ohm) that are desirable for input and output circuits of present and future contemplated generations of sub-micron bipolar/BiCMOS circuit processes.

Abstract: The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz->2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the NPN transistor.

Abstract: One embodiment of the instant invention is an electrostatic discharge protection device (10) which includes a field-effect transistor, the field-effect transistor comprising: a substrate (12) of a first conductivity type and having a surface and a backside; a gate structure (18) insulatively disposed on the substrate; a blocking region (30) disposed on the substrate and adjacent to the gate structure; a lightly-doped region (32) of a second conductivity type opposite the first conductivity type and disposed within the substrate and beneath the blocking region; a channel region (14) disposed within the substrate, under the gate structure, and adjacent the lightly-doped region; a first doped region (38) of the second conductivity type and disposed within the substrate and adjacent to the lightly doped region, the first doped region spaced away from the channel region by the lightly-doped region; and a second doped region (22) of the second conductivity type and disposed within the substrate, the second doped re