Patents by Inventor Ajith E. Amerasekera

Ajith E. Amerasekera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing
    Patent number: 6873506
    Abstract: The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10) comprising at least one input element (20) is protected by a protective circuit (40). The protective circuit (40) is operable to protect the integrated circuit (10) from damage due to electrostatic discharge and may be coupled to the input element (20). The protective circuit (40) comprises a lateral NPN transistor (T1) coupled to the input element (20) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (20). The protective circuit (40) also may comprise a lateral PNP transistor (T2) coupled to the input element (20) and to the lateral NPN transistor (T1). The lateral PNP transistor (T2) is operable to aid in raising a potential of the base of the lateral NPN transistor (T1).
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: March 29, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Zhiliang Julian Chen, Thomas A. Vrotsos, Ajith E. Amerasekera
  • System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing
    Publication number: 20040047094
    Abstract: The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10) comprising at least one input element (20) is protected by a protective circuit (40). The protective circuit (40) is operable to protect the integrated circuit (10) from damage due to electrostatic discharge and may be coupled to the input element (20). The protective circuit (40) comprises a lateral NPN transistor (T1) coupled to the input element (20) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (20). The protective circuit (40) also may comprise a lateral PNP transistor (T2) coupled to the input element (20) and to the lateral NPN transistor (T1). The lateral PNP transistor (T2) is operable to aid in raising a potential of the base of the lateral NPN transistor (T1).
    Type: Application
    Filed: September 5, 2003
    Publication date: March 11, 2004
    Inventors: Zhiliang Julian Chen, Thomas A. Vrotsos, Ajith E. Amerasekera