Patents by Inventor Ajith Harihara Subramonia

Ajith Harihara Subramonia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Improving routability of integrated circuit design without impacting the design area
    Patent number: 8127263
    Abstract: Improving routability of an integrated circuit (IC) design without impacting the area is described. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: February 28, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Pavan Vithal Torvi, Girishankar Gurumurthy, Dharin N Shah, Ajith Harihara Subramonia
  • ROUTABILITY OF INTEGRATED CIRCUIT DESIGN WITHOUT IMPACTING THE AREA
    Publication number: 20100199252
    Abstract: Improving the routability of integrated circuit (IC) design without impacting the area. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.
    Type: Application
    Filed: February 3, 2009
    Publication date: August 5, 2010
    Inventors: Pavan Vithal Torvi, Girishankar Gurumurthy, Dharin N. Shah, Ajith Harihara Subramonia