Patents by Inventor Ajith Varghese
Ajith Varghese has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9054056Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.Type: GrantFiled: August 5, 2014Date of Patent: June 9, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
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Patent number: 9029251Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.Type: GrantFiled: August 5, 2014Date of Patent: May 12, 2015Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
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Publication number: 20140339609Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.Type: ApplicationFiled: August 5, 2014Publication date: November 20, 2014Inventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
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Publication number: 20140342521Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.Type: ApplicationFiled: August 5, 2014Publication date: November 20, 2014Inventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
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Patent number: 8828855Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.Type: GrantFiled: April 30, 2007Date of Patent: September 9, 2014Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
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Patent number: 8119470Abstract: Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.Type: GrantFiled: March 21, 2007Date of Patent: February 21, 2012Assignee: Texas Instruments IncorporatedInventors: Shashank Sureshchandra Ekbote, Borna Obradovic, Lindsey Hall, Craig Huffman, Ajith Varghese
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Patent number: 7855111Abstract: Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.Type: GrantFiled: August 7, 2009Date of Patent: December 21, 2010Assignee: Texas Instruments IncorporatedInventors: Haowen Bu, Shaofeng Yu, Angelo Pinto, Ajith Varghese
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Patent number: 7838370Abstract: A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a bis-(t-butylamino)silane-based nitride liner layer within the isolation trench, which exhibits a five-fold greater resistance to nitride etching solutions as compared with DCS nitride, thereby allowing protection against damage from unintended over-etching. The bis-(t-butylamino)silane-based nitride layer also exerts a greater tensile strain on moat regions that results in heightened carrier mobility of active regions, thereby increasing the performance of NMOS transistors embedded therein.Type: GrantFiled: December 27, 2007Date of Patent: November 23, 2010Assignee: Texas Instruments IncorporatedInventors: Narendra Singh Mehta, Wayne Anthony Bather, Ajith Varghese
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Patent number: 7723173Abstract: A method for preventing oxidation in a high-k dielectric/metal gate stack in the manufacture of an integrated circuit device is disclosed. In a detailed embodiment, a PMOS region stack has nitrided hafnium silicide, tungsten, tantalum nitride and polysilicon layers. An NMOS region stack has nitrided hafnium silicide, tungsten silicide, tantalum nitride and polysilicon layers. A thin polysilicon layer deposited over the stacks is converted to an oxide using a low temperature ultraviolet ozone oxidation process or a plasma nitridation using decoupled plasma nitridation or NH3 annealing. The oxide provides a coating over the top and sides of the stacks to protect metal and interfaces from oxidation.Type: GrantFiled: March 9, 2009Date of Patent: May 25, 2010Assignee: Texas Instruments IncorporatedInventors: Ajith Varghese, James J. Chambers
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Patent number: 7696021Abstract: A method of manufacturing a semiconductor device including calibrating an ion implant process. The calibration includes forming a dielectric layer over a calibration substrate. A dopant is implanted into the dielectric layer. Charge is deposited on a surface of the dielectric layer, and voltage on the surface is measured. An electrical characteristic of the dielectric layer is determined, and a doping level of the dielectric layer is determined from the electrical characteristic. The electrical characteristic is associated with an operating set-point of the ion implant process. The calibrated ion implant process is used to implant the dopant into a semiconductor substrate.Type: GrantFiled: November 13, 2006Date of Patent: April 13, 2010Assignee: Texas Instruments IncorporatedInventors: Narendra Singh Mehta, Ajith Varghese, Benjamin Moser
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Patent number: 7682988Abstract: A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.Type: GrantFiled: August 31, 2004Date of Patent: March 23, 2010Assignee: Texas Instruments IncorporatedInventors: Husam N. Alshareef, Rajesh Khamankar, Ajith Varghese, Cathy A. Chancellor, Anand Krishnan, Malcolm J. Bevan
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Publication number: 20100032727Abstract: Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.Type: ApplicationFiled: August 7, 2009Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Haowen Bu, Shaofeng Yu, Angelo Pinto, Ajith Varghese
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Publication number: 20090170346Abstract: A method for preventing oxidation in a high-k dielectric/metal gate stack in the manufacture of an integrated circuit device is disclosed. In a detailed embodiment, a PMOS region stack has nitrided hafnium silicide, tungsten, tantalum nitride and polysilicon layers. An NMOS region stack has nitrided hafnium silicide, tungsten silicide, tantalum nitride and polysilicon layers. A thin polysilicon layer deposited over the stacks is converted to an oxide using a low temperature ultraviolet ozone oxidation process or a plasma nitridation using decoupled plasma nitridation or NH3 annealing. The oxide provides a coating over the top and sides of the stacks to protect metal and interfaces from oxidation.Type: ApplicationFiled: March 9, 2009Publication date: July 2, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ajith Varghese, James J. Chambers
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Patent number: 7514308Abstract: The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).Type: GrantFiled: May 8, 2007Date of Patent: April 7, 2009Assignee: Texas Instruments IncorporatedInventors: Ajith Varghese, Husam N. Alshareef, Rajesh Khamankar
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Publication number: 20090045472Abstract: A semiconductor device includes source/drain regions formed in a substrate and having a concentration of nitrogen of at least about 5E18 cm?3. A gate dielectric is located over the substrate and between the source/drain regions. Gate sidewall spacers are located over said source/drain regions. A nitrogen-doped electrode including polysilicon is located over the gate dielectric. The electrode has a concentration of nitrogen therein greater than the concentration of nitrogen in the source/drain regions.Type: ApplicationFiled: August 13, 2007Publication date: February 19, 2009Applicant: Texas Instruments IncorporatedInventors: Srinivasan Chakravarthi, Narendra Singh Mehta, Rajesh Khamankar, Ajith Varghese, Malcolm J. Bevan, Tad Grider
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Publication number: 20080315324Abstract: The present invention, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the substrate 115 and having a thickness less than a thickness of the first gate dielectric layer 160, and subjecting the first and second gate dielectric layers 160, 165 to a second nitridation process, wherein the first and second nitridation processes are different. The present invention also provides a microelectronics device 100 fabricated in accordance with the method.Type: ApplicationFiled: September 4, 2008Publication date: December 25, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: AJITH VARGHESE, REIMA T. LAAKSONEN, TERRENCE J. RILEY
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Publication number: 20080268603Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.Type: ApplicationFiled: April 30, 2007Publication date: October 30, 2008Inventors: Hiroaki NIIMI, Jarvis Benjamin Jacobs, Ajith Varghese
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Publication number: 20080268627Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.Type: ApplicationFiled: April 30, 2007Publication date: October 30, 2008Inventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
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Publication number: 20080251864Abstract: A method for implementing a stacked gate, comprising forming a gate dielectric on a semiconductor body, forming a first layer of gate electrode material on the gate dielectric, forming a second layer of gate electrode material on the first layer of gate electrode material, wherein the grain size distribution of the first layer of gate electrode material is different than the grain size distribution of the second layer of gate electrode material, implanting the first and second gate electrode materials, patterning the first and the second gate electrodes and the gate dielectric, and forming source and drain regions.Type: ApplicationFiled: April 11, 2007Publication date: October 16, 2008Inventors: Yuanning Chen, Stephanie W. Butler, Ajith Varghese, Narendra Singh Mehta
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Patent number: 7435651Abstract: The present invention, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the substrate 115 and having a thickness less than a thickness of the first gate dielectric layer 160, and subjecting the first and second gate dielectric layers 160,165 to a second nitridation process, wherein the first and second nitridation processes are different. The present invention also provides a microelectronics device 100 fabricated in accordance with the method.Type: GrantFiled: September 12, 2005Date of Patent: October 14, 2008Assignee: Texas Instruments IncorporatedInventors: Ajith Varghese, Reima T. Laaksonen, Terrence J. Riley