Abstract: Systems and methods for on-demand unicast forwarding in a high performance computing environment, in accordance with an embodiment. An exemplary method can provide, at a computer comprising one or more microprocessors, a plurality of switches, a plurality of host channel adapters, and a plurality of hosts. The method can provide, at two rails, redundant connectivity between the plurality of hosts, wherein each rail comprises a set of the plurality of switches. The method can detect a disruption i connectivity between two hosts of the plurality of hosts. The method can re-establish communication between the two hosts of the plurality of hosts via unicast packets on an inter-rail link, the inter-rail link being provided between the two rails.

Abstract: Systems and methods for using InfiniBand routing algorithms for Ethernet fabrics in a high performance computing environment. The method can provide, at a computer comprising one or more microprocessors, a plurality of switches, a plurality of hosts, a topology provider (TP) module, a routing engine (RE) module, and a switch initializer (SI) module. The method can perform a discovery sweep, by the TP, of the plurality of hosts and the plurality of switches and assigns an address to each of the plurality of hosts and the plurality of switches. The method can calculate, by the routing engine, a routing map, based upon a routing scheme, for the plurality of hosts and the plurality of switches, the routing map comprising a plurality of forwarding tables. The method can configure, each of the plurality of switches with a forwarding table of the plurality of forwarding tables calculated by the routing engine.

Abstract: A system and method can support efficient packet processing in a network environment. The system can comprise a direct memory access (DMA) resources pool that comprises one or more of DMA resources. Furthermore, the system can use a plurality of packet buffers in a memory, wherein each said DMA resource can point to a chain of packet buffers in the memory. Here, the chain of packet buffers can be implemented based on either a linked list data structure and/or a linear array data structure. Additionally, each said DMA resource allows a packet processing thread to access the chain of packet buffers using a pre-assigned thread key.

Abstract: A system and method can support efficient packet processing in a network environment. The system can comprise a thread scheduling engine that operates to assign a thread key to each software thread in a plurality of software threads. Furthermore, the system can comprise a pool of direct memory access (DMA) resources that can be used to process packets in the network environment. Additionally, each said software thread operates to request access to a DMA resource in the pool of DMA resources by presenting an assigned thread key, and a single software thread is allowed to access multiple DMA resources using the same thread key.

Abstract: A system and method can support efficient packet processing in a network environment. The system can comprise a thread scheduling engine that operates to assign a thread key to each software thread in a plurality of software threads. Furthermore, the system can comprise a pool of direct memory access (DMA) resources that can be used to process packets in the network environment. Additionally, each said software thread operates to request access to a DMA resource in the pool of DMA resources by presenting an assigned thread key, and a single software thread is allowed to access multiple DMA resources using the same thread key.

Abstract: A system and method can support efficient packet processing in a network environment. The system can comprise a direct memory access (DMA) resources pool that comprises one or more of DMA resources. Furthermore, the system can use a plurality of packet buffers in a memory, wherein each said DMA resource can point to a chain of packet buffers in the memory. Here, the chain of packet buffers can be implemented based on either a linked list data structure and/or a linear array data structure. Additionally, each said DMA resource allows a packet processing thread to access the chain of packet buffers using a pre-assigned thread key.

Abstract: Disclosed are systems and methods for reclaiming posted buffers during a direct memory access (DMA) operation executed by an input/output device (I/O device) in connection with data transfer across a network. During the data transfer, the I/O device may cancel a buffer provided by a device driver thereby relinquishing ownership of the buffer. A condition for the I/O device relinquishing ownership of a buffer may be provided by a distance vector that may be associated with the buffer. The distance vector may specify a maximum allowable distance between the buffer and a buffer that is currently fetched by the I/O device. Alternatively, a condition for the I/O device relinquishing ownership of a buffer may be provided by a timer. The timer may specify a maximum time that the I/O device may maintain ownership of a particular buffer. In other implementations, a mechanism is provided to force the I/O device to relinquish some or all of the buffers that it controls.

Abstract: Disclosed are systems and methods for reclaiming posted buffers during a direct memory access (DMA) operation executed by an input/output device (I/O device) in connection with data transfer across a network. During the data transfer, the I/O device may cancel a buffer provided by a device driver thereby relinquishing ownership of the buffer. A condition for the I/O device relinquishing ownership of a buffer may be provided by a distance vector that may be associated with the buffer. The distance vector may specify a maximum allowable distance between the buffer and a buffer that is currently fetched by the I/O device. Alternatively, a condition for the I/O device relinquishing ownership of a buffer may be provided by a timer. The timer may specify a maximum time that the I/O device may maintain ownership of a particular buffer. In other implementations, a mechanism is provided to force the I/O device to relinquish some or all of the buffers that it controls.