Patents by Inventor Ak R. Ahmed

Ak R. Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory cell write
    Patent number: 8345491
    Abstract: Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventors: Satish K. Damaraju, Ak R. Ahmed, Scott E. Siers
  • MEMORY CELL WRITE
    Publication number: 20120039135
    Abstract: Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed.
    Type: Application
    Filed: October 26, 2011
    Publication date: February 16, 2012
    Inventors: Satish K. Damaraju, Ak R. Ahmed, Scott E. Siers
  • Memory cell write
    Patent number: 8050116
    Abstract: Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: November 1, 2011
    Assignee: Intel Corporation
    Inventors: Satish K. Damaraju, Ak R. Ahmed, Scott E. Siers
  • MEMORY CELL WRITE
    Publication number: 20110069566
    Abstract: Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed.
    Type: Application
    Filed: September 22, 2009
    Publication date: March 24, 2011
    Inventors: Satish K. Damaraju, Ak R. Ahmed, Scott E. Siers
  • Circuit technique to reduce leakage during reduced power mode
    Patent number: 7805619
    Abstract: Provided herein are schemes for reducing leakage in dynamic circuits during sleep modes.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: September 28, 2010
    Assignee: Intel Corporation
    Inventors: John R. Cherukuri, Ak R. Ahmed, Arun Subbiah, Satish Damaraju