Patents by Inventor Akane Aizaki

Akane Aizaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5121007
    Abstract: A step-down circuit is incorporated in a large scale integrated circuit for producing an internal power voltage from an external power voltage, and the step-down circuit comprises a reference signal generating unit for producing a reference signal indicative of a target level for the internal power voltage, first and second voltage regulating units for regulating the internal power voltage to the target level, and a monitoring unit monitoring the voltage level of the power voltage and producing an enable signal in the standby mode of operation when the external power voltage exceeds a predetermined level, wherein the first and second voltage regulating units are selectively enabled depending upon mode of the large scale integrated circuit, i.e. an active mode and a standby mode, as well as the level of the external power voltage so that power consumption of the large scale integrated circuit is improved.
    Type: Grant
    Filed: April 29, 1991
    Date of Patent: June 9, 1992
    Assignee: NEC Corporation
    Inventor: Akane Aizaki
  • Patent number: 5115434
    Abstract: A different power sources interface circuit for connecting a first power source operating circuit for supplying complementary outputs with a second power source operating circuit having a power source for supplying a voltage higher than that of the power source of the first power source circuit comprises an input transistor circuit including first and second N channel MOS transistors which are in series connected between said second power source and a ground and have respective gates to which the complementary outputs of said first power circuit are supplied; a first inverter circuit having an input connected with a connection between both said transistors; and a second inverter circuit having an input and an output thereof which are connected with the output and input of said first inverter circuit, respectively.
    Type: Grant
    Filed: February 6, 1991
    Date of Patent: May 19, 1992
    Assignee: NEC Corporation
    Inventor: Akane Aizaki