Abstract: A semiconductor memory device provided with an improved system for detecting an address of a defective column or row of memory cells replaced by a redundant column or row of memory cells through an output port comprises normal memory cells, at least one redundant memory cell, a power-on detection for generating a detection signal when a power supply to the memory circuit is switched on, a first circuit for initializing the normal memory cells at a first logic state in response to the detection signal, and a second circuit for initializing the redundant memory cell at a second logic state different from the first logic state in response to the detection signal.