Abstract: A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array.

Abstract: A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip having a memory controller. The memory controller includes a memory interface circuit configured to interface the IC chip with a memory chip having a memory array, and a first control circuit. The memory chip has a configuration circuit for adjusting one or more configurations of the memory chip. The first control circuit is configured to control the memory interface circuit and to communicate with the configuration circuit in the memory chip via the memory interface circuit to adjust the one or more configurations of the memory chip.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip having a memory controller. The memory controller includes a memory interface circuit configured to interface the IC chip with a memory chip having a memory array, and a first control circuit. The memory chip has a configuration circuit for adjusting one or more configurations of the memory chip. The first control circuit is configured to control the memory interface circuit and to communicate with the configuration circuit in the memory chip via the memory interface circuit to adjust the one or more configurations of the memory chip.