Abstract: In one embodiment, a bounding box prefetch unit in a microprocessor, the bounding box prefetch unit comprising: storage comprising a plurality of active prefetcher state entries for storing state information for a corresponding plurality of access streams associated with load requests, and a corresponding plurality of prediction logic; and a prefetcher state cache comprising plural prefetcher state entries that do not match any of the active prefetcher state entries.

Abstract: In one embodiment, a bounding box prefetch unit in a microprocessor, the bounding box prefetch unit comprising: storage comprising a plurality of active prefetcher state entries for storing state information for a corresponding plurality of access streams associated with load requests, and a corresponding plurality of prediction logic; and a prefetcher state cache comprising plural prefetcher state entries that do not match any of the active prefetcher state entries.

Abstract: Methods and apparatus are provided to implement a unique quasi least recently used (LRU) implementation of an n-way set-associative cache. In accordance with one implementation, a method determines to generate a prefetch request, obtains a confidence value for target data associated with the prefetch request, writes the target data into a set of the n-way set associative cache memory, modifies an n-position array of the cache memory, such that a particular one of n array positions identifies one of the n ways, wherein the particular one of the n LRU array positions is determined by the confidence value.