Patents by Inventor Akarsh Joshi

Akarsh Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11527991
    Abstract: A voltage controlled oscillator (VCO) circuitry includes a varactor array. The varactor array includes a first varactor unit including a first varactor, a second varactor, and first switch circuitry. The first varactor is connected to a first node and a second node, and the second varactor is connected to the second node and a third node. The second node receives a voltage control signal. The first switch circuitry is electrically coupled to the first node and the third node, and selectively electrically couples a first voltage signal to the first node and the third node based on a first control signal.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: December 13, 2022
    Assignee: Synopsys, Inc.
    Inventors: Akarsh Joshi, Biman Chattopadhyay
  • Publication number: 20220166381
    Abstract: A voltage controlled oscillator (VCO) circuitry includes a varactor array. The varactor array includes a first varactor unit including a first varactor, a second varactor, and first switch circuitry. The first varactor is connected to a first node and a second node, and the second varactor is connected to the second node and a third node. The second node receives a voltage control signal. The first switch circuitry is electrically coupled to the first node and the third node, and selectively electrically couples a first voltage signal to the first node and the third node based on a first control signal.
    Type: Application
    Filed: November 22, 2021
    Publication date: May 26, 2022
    Inventors: Akarsh JOSHI, Biman CHATTOPADHYAY
  • Patent number: 10749531
    Abstract: A multi-modulus frequency divider circuit includes first and second frequency division stages. The first frequency division stage receives a first input clock signal having a first oscillating frequency, a first modulus input signal, and a first division bit. The first frequency division stage divides the first oscillating frequency by a first division ratio, and generates a second input clock signal having a second oscillating frequency. The second frequency division stage receives the second input clock signal, a second modulus input signal, and a second division bit. The second frequency division stage generates an output clock signal having an output oscillating frequency by dividing the second oscillating frequency by a second division ratio.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 18, 2020
    Assignee: Synopsys, Inc.
    Inventors: Sanket Naik, Akarsh Joshi, Gopal Krishna Ullal Nayak
  • Patent number: 10715158
    Abstract: A phase-locked loop (PLL) for generating a VCO output signal at a target frequency has been disclosed. The PLL includes at least first and second VCOs, first and second multiplexers, and a frequency divider. The first and second VCOs generate first and second output signals over first and second frequency ranges, respectively. The first multiplexer receives the first and second output signals from the first and second VCOs, respectively, and outputs the first output signal when the target frequency is in the first frequency range and the second output signal when the target frequency is in the second frequency range or less than the first frequency range. The frequency divider divides a frequency of the second output signal by a division factor to generate a third output signal. The second multiplexer outputs one of the first, second, and third output signals as the VCO output signal.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: July 14, 2020
    Assignee: Synopsys, Inc.
    Inventors: Akarsh Joshi, Sharath Nadsar, Biman Chattopadhyay