Patents by Inventor Akash Bangalore Srinivasa

Akash Bangalore Srinivasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wordline driver architecture
    Patent number: 11688444
    Abstract: Various implementations described herein are directed to a device having first circuitry with wordline drivers coupled to wordlines. The device may have second circuitry with switch structures that are coupled between a first voltage and ground. The switch structures may be configured to provide a second voltage to a power connection of each wordline driver based on the first voltage.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: June 27, 2023
    Assignee: Arm Limited
    Inventors: Akash Bangalore Srinivasa, Andy Wangkun Chen, Yew Keong Chong, Sreebin Sreedhar, Balaji Ravikumar, Penaka Phani Goberu, Vibin Vincent
  • Memory architecture with pulsed-bias power
    Patent number: 11468941
    Abstract: Various implementations described herein are related to a device having memory circuitry with an array of bitcells coupled to a power rail. The device may have pulse-bias circuitry with stacks of transistors that are coupled to the power rail. In various instances, the stacks of transistors may be alternately activated so as to thereby provide a pulse-biased power supply to the array of bitcells via the power rail.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: October 11, 2022
    Assignee: Arm Limited
    Inventors: Akash Bangalore Srinivasa, Andy Wangkun Chen, Penaka Phani Goberu, Yew Keong Chong
  • Wordline Driver Architecture
    Publication number: 20220310144
    Abstract: Various implementations described herein are directed to a device having first circuitry with wordline drivers coupled to wordlines. The device may have second circuitry with switch structures that are coupled between a first voltage and ground. The switch structures may be configured to provide a second voltage to a power connection of each wordline driver based on the first voltage.
    Type: Application
    Filed: March 23, 2021
    Publication date: September 29, 2022
    Inventors: Akash Bangalore Srinivasa, Andy Wangkun Chen, Yew Keong Chong, Sreebin Sreedhar, Balaji Ravikumar, Penaka Phani Goberu, Vibin Vincent
  • Memory Architecture with Pulsed-Bias Power
    Publication number: 20220284942
    Abstract: Various implementations described herein are related to a device having memory circuitry with an array of bitcells coupled to a power rail. The device may have pulse-bias circuitry with stacks of transistors that are coupled to the power rail. In various instances, the stacks of transistors may be alternately activated so as to thereby provide a pulse-biased power supply to the array of bitcells via the power rail.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 8, 2022
    Inventors: Akash Bangalore Srinivasa, Andy Wangkun Chen, Penaka Phani Goberu, Yew Keong Chong
  • Write assist circuitry
    Patent number: 11043262
    Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 22, 2021
    Assignee: Arm Limited
    Inventors: Arjunesh Namboothiri Madhavan, Akash Bangalore Srinivasa, Sujit Kumar Rout, Vikash, Gaurav Rattan Singla, Vivek Nautiyal, Shri Sagar Dwivedi, Jitendra Dasani, Lalit Gupta
  • Write Assist Circuitry
    Publication number: 20190237135
    Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 1, 2019
    Inventors: Arjunesh Namboothiri Madhavan, Akash Bangalore Srinivasa, Sujit Kumar Rout, Vikash, Gaurav Rattan Singla, Vivek Nautiyal, Shri Sagar Dwivedi, Jitendra Dasani, Lalit Gupta