Patents by Inventor Akash Sharma

Akash Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071403
    Abstract: According to one embodiment, a method, computer system, and computer program product for front-end clipping reduction is provided. The embodiment may include initiating an audio interaction. The embodiment may also include predicting a change in network connectivity within the audio interaction. The embodiment may further include, in response to the predicted change in network connectivity, determining whether to perform a voice clarity improvement. The embodiment may also include, in response to determining to perform the voice clarity improvement, performing the voice clarity improvement for the audio interaction.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Sarbajit K. Rakshit, Shailendra Moyal, Akash U. Dhoot, Nitika Sharma
  • Patent number: 10996723
    Abstract: A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: May 4, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Quang Nguyen, Duc Dang, Raju Joshi, David Abada, Akash Sharma, Zhanhe Shi
  • Patent number: 10430745
    Abstract: The present invention is directed towards a method for evaluating driver performance. In exemplary embodiments, the method comprises receiving driver activity associated with a driver of a vehicle in a fleet, determining a driver score based on predetermined criteria and generating and updating a driver profile based on the driver activity and evaluating the driver score to generate rewards for the driver and updating the driver profile accordingly.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: October 1, 2019
    Assignee: Azuga, Inc.
    Inventors: Ananth Rani, Ashwin Sabapathy, Mahesh Kumar, Akash Sharma
  • Publication number: 20170323244
    Abstract: The present invention is directed towards a method for evaluating driver performance. In exemplary embodiments, the method comprises receiving driver activity associated with a driver of a vehicle in a fleet, determining a driver score based on predetermined criteria and generating and updating a driver profile based on the driver activity and evaluating the driver score to generate rewards for the driver and updating the driver profile accordingly.
    Type: Application
    Filed: May 3, 2017
    Publication date: November 9, 2017
    Inventors: Ananth Rani, Ashwin Sabapathy, Mahesh Kumar, Akash Sharma
  • Patent number: 9495492
    Abstract: An apparatus and method for implementing synchronous triggers for waveform capture in a multiple FPGA system is described. The apparatus includes trigger net circuitry that has one or more trigger nets and an output. Furthermore, a plurality of programmable logic devices are provided with each logic device including logic circuitry that is programmable to correspond to a circuit design, a logic analyzer circuit that includes logic connections coupled to the logic circuitry to monitor operating signals of the circuit design, and a register with a data input that is coupled to the output of the trigger net circuitry and an output that is coupled to a control input of the logic analyzer circuit. The trigger net circuitry outputs a control signal that is applied to all registers such that each logic analyzer circuit is controlled to concurrently capture data waveforms.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: November 15, 2016
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Vasant V. Ramabadran, Akash Sharma